Datasheet > PCA9601DP,118

PCA9601DP,118

更新时间： 2024-01-14 18:11:01

品牌	Logo	应用领域
恩智浦 - NXP		PC 光电二极管逻辑集成电路
页数	文件大小	规格书
32页	347K
描述
PCA9601 - Dual bidirectional bus buffer TSSOP 8-Pin

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PCA9601DP,118 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	TSSOP	包装说明：	TSSOP,
针数：	8	Reach Compliance Code：	compliant
风险等级：	1.74	系列：	PCA9
JESD-30 代码：	S-PDSO-G8	长度：	3 mm
逻辑集成电路类型：	BUS TRANSCEIVER	湿度敏感等级：	1
位数：	1	功能数量：	2
端口数量：	2	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	OPEN-COLLECTOR	输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	SQUARE	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	1.1 mm
最大供电电压 (Vsup)：	15 V	最小供电电压 (Vsup)：	2.5 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	3 mm
Base Number Matches：	1

PCA9601DP,118 数据手册

PCA9601

Dual bidirectional bus buffer

Rev. 3 — 24 September 2015

Product data sheet

1. General description

The PCA9601 is designed to isolate I²C-bus capacitance, allowing long buses to be

driven in point-to-point or multipoint applications of up to 4000 pF. The PCA9601 is a

higher-speed version of the P82B96 and a higher drive version of the PCA9600 that

allows many more Fast-mode Plus (Fm+) slaves on remote daughter cards in applications

with temperature range of 0 C to 85 C.

It creates a non-latching, bidirectional, logic interface between a normal I²C-bus and a

range of other higher capacitance or different voltage bus configurations. It can operate at

speeds up to at least 1 MHz, and the high drive side is compatible with the Fast-mode

Plus specifications.

The PCA9601 features temperature-stabilized logic voltage levels at its SX/SY interface

making it suitable for interfacing with buses that have non I²C-bus-compliant logic levels

such as SMBus, PMBus, or with microprocessors that use those same TTL logic levels.

15 mA drive capability over 0 C to 85 C at SX/SY allows driving a 5 V Fm+ bus with

470 pF loading.

The separation of the bidirectional I²C-bus signals into unidirectional TX and RX signals

enables the SDA and SCL signals to be transmitted via balanced transmission lines

(twisted pairs), or with galvanic isolation using opto or magnetic coupling. The TX and RX

signals may be connected together to provide a normal bidirectional signal.

2. Features and benefits

 Bidirectional data transfer of I²C-bus signals

 15 mA SX/SY sink capability yields 5 V Fm+ bus rise time with 470 pF loads

 Isolates capacitance allowing > 400 pF on SX/SY side and 4000 pF on TX/TY side

 1 MHz operation on up to 20 meters of wire (see AN10658)

 Supply voltage range of 2.5 V to 15 V with I²C-bus logic levels on SX/SY side

independent of supply voltage

 Splits I²C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface

with opto-electrical isolators and similar devices that need unidirectional input and

output signal paths

 Low power supply current

 ESD protection exceeds 3500 V HBM per JESD22-A114, and 1400 V CDM per

JESD22-C101

 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

 Packages offered: SO8 and TSSOP8 (MSOP8)

12 3 4 5 6 7...32

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