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PCA9534PW PDF预览

PCA9534PW

更新时间: 2024-01-20 19:57:35
品牌 Logo 应用领域
德州仪器 - TI 并行IO端口微控制器和处理器外围集成电路光电二极管输出元件
页数 文件大小 规格书
32页 658K
描述
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS

PCA9534PW 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFN
包装说明:QFN-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.82Is Samacsys:N
最大时钟频率:0.4 MHzJESD-30 代码:S-PQCC-N16
JESD-609代码:e4长度:4 mm
湿度敏感等级:2位数:8
I/O 线路数量:8端口数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC16,.16SQ,25
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:2.5/5 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:Parallel IO Ports最大压摆率:0.175 mA
最大供电电压:5.5 V最小供电电压:2.3 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4 mm
uPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches:1

PCA9534PW 数据手册

 浏览型号PCA9534PW的Datasheet PDF文件第5页浏览型号PCA9534PW的Datasheet PDF文件第6页浏览型号PCA9534PW的Datasheet PDF文件第7页浏览型号PCA9534PW的Datasheet PDF文件第9页浏览型号PCA9534PW的Datasheet PDF文件第10页浏览型号PCA9534PW的Datasheet PDF文件第11页 
PCA9534  
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER  
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS  
www.ti.com  
SCPS124BSEPTEMBER 2006REVISED FEBRUARY 2007  
Interrupt Output (INT)  
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the  
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original  
setting, data is read from the port that generated the interrupt or in a Stop event. Resetting occurs in the read  
mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. In a  
Stop event, INT is cleared after the rising edge of SDA. Interrupts that occur during the ACK or NACK clock  
pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the  
I/Os after resetting is detected and is transmitted as INT.  
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output  
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the  
state of the pin does not match the contents of the Input Port register.  
The INT output has an open-drain structure and requires pull-up resistor to VCC  
.
Bus Transactions  
Data is exchanged between the master and PCA9534 through write and read commands.  
Writes  
Data is transmitted to the PCA9534 by sending the device address and setting the least-significant bit to a logic  
0 (see Figure 4 for device address). The command byte is sent after the address and determines which register  
receives the data that follows the command byte (see Figure 6 and Figure 7). There is no limitation on the  
number of data bytes sent in one write transmission.  
SCL  
1
2
3
4
5
6
7
8
9
Slave Address  
Command Byte  
Data to Port  
Data 1  
S
0
1
0
0 A2 A1 A0  
0
A
0
0
0
0
0
0
0
1
A
A
P
SDA  
ACK From Slave  
ACK From Slave  
R/W ACK From Slave  
Start Condition  
Write to Port  
Data Out  
From Port  
Data 1 Valid  
t
pv  
Figure 6. Write to Output Port Register  
<br/>  
SCL  
1
2
3
4
5
6
7
8
0
9
Slave Address  
Command Byte  
Data to Register  
Data  
SDA  
S
0
1
0
0 A2 A1 A0  
A
0
0
0
0
0
0
1
1/0  
A
A
P
Start Condition  
R/W ACK From Slave  
ACK From Slave  
ACK From Slave  
Data to  
Register  
Figure 7. Write to Configuration or Polarity Inversion Registers  
8
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PCA9534PW 替代型号

型号 品牌 替代类型 描述 数据表
PCA9534PW TI

当前型号

REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION
PCA9557PWR TI

完全替代

REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH RESET AND CONFIGURATION REGISTERS
PCA9534APWR TI

完全替代

REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION

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