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PCA9534PW PDF预览

PCA9534PW

更新时间： 2024-01-28 09:11:37
品牌 Logo 应用领域
德州仪器 - TI 并行IO端口微控制器和处理器外围集成电路光电二极管输出元件
页数 文件大小 规格书
32页 658K
描述
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS

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PCA9534PW 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFN
包装说明：QFN-16针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.82Is Samacsys：N
最大时钟频率：0.4 MHzJESD-30 代码：S-PQCC-N16
JESD-609代码：e4长度：4 mm
湿度敏感等级：2位数：8
I/O 线路数量：8端口数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC16,.16SQ,25
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：2.5/5 V
认证状态：Not Qualified座面最大高度：1 mm
子类别：Parallel IO Ports最大压摆率：0.175 mA
最大供电电压：5.5 V最小供电电压：2.3 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：NO LEAD
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4 mm
uPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches：1

PCA9534PW 数据手册

 浏览型号PCA9534PW的Datasheet PDF文件第4页浏览型号PCA9534PW的Datasheet PDF文件第5页浏览型号PCA9534PW的Datasheet PDF文件第6页浏览型号PCA9534PW的Datasheet PDF文件第8页浏览型号PCA9534PW的Datasheet PDF文件第9页浏览型号PCA9534PW的Datasheet PDF文件第10页 
PCA9534  
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER  
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS  
www.ti.com  
SCPS124B–SEPTEMBER 2006–REVISED FEBRUARY 2007  
Command Byte  
CONTROL  
REGISTER BITS  
COMMAND  
BYTE (HEX)  
POWER-UP  
DEFAULT  
REGISTER  
PROTOCOL  
B1  
0
B0  
0
0x00  
0x01  
0x02  
0x03  
Input Port  
Output Port  
Read byte  
xxxx xxxx  
1111 1111  
0000 0000  
1111 1111  
0
1
Read/write byte  
Read/write byte  
Read/write byte  
1
0
Polarity Inversion  
Configuration  
1
1
Register Descriptions  
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is  
defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these  
registers have no effect. The default value, X, is determined by the externally applied logic level.  
Before a read operation, a write transmission is sent with the command byte to let the I2C device know that the  
Input Port register will be accessed next.  
Register 0 (Input Port Register)  
BIT  
I7  
X
I6  
X
I5  
X
I4  
X
I3  
X
I2  
X
I1  
X
I0  
X
DEFAULT  
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the  
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this  
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.  
Register 1 (Output Port Register)  
BIT  
O7  
1
O6  
1
O5  
1
O4  
1
O3  
1
O2  
1
O1  
1
O0  
1
DEFAULT  
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration  
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this  
register is cleared (written with a 0), the corresponding port pin original polarity is retained.  
Register 2 (Polarity Inversion Register)  
BIT  
N7  
0
N6  
0
N5  
0
N4  
0
N3  
0
N2  
0
N1  
0
N0  
0
DEFAULT  
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,  
the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is  
cleared to 0, the corresponding port pin is enabled as an output.  
Register 3 (Configuration Register)  
BIT  
C7  
1
C6  
1
C5  
1
C4  
1
C3  
1
C2  
1
C1  
1
C0  
1
DEFAULT  
Power-On Reset  
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9534 in a reset condition  
until VCC has reached VPOR. At that point, the reset condition is released and the PCA9534 registers and  
I2C/SMBus state machine will initialize to their default states. After that, VCC must be lowered to below 0.2 V and  
then back up to the operating voltage for a power-reset cycle.  
7
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