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PCA9506DGG,512

更新时间: 2024-02-06 05:49:16
品牌 Logo 应用领域
恩智浦 - NXP PC光电二极管外围集成电路
页数 文件大小 规格书
34页 264K
描述
PCA9505/06 - 40-bit I2C-bus I/O port with RESET, OE and INT TSSOP 56-Pin

PCA9506DGG,512 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP56,.3,20
针数:56Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:7.94
JESD-30 代码:R-PDSO-G56JESD-609代码:e4
长度:14 mm湿度敏感等级:3
位数:40I/O 线路数量:8
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2.5/5 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Parallel IO Port
最大供电电压:5.5 V最小供电电压:2.3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:6.1 mm
uPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches:1

PCA9506DGG,512 数据手册

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PCA9505/06  
NXP Semiconductors  
40-bit I2C-bus I/O port with RESET, OE and INT  
Table 2.  
Pin description …continued  
Symbol  
Pin  
Type  
Description  
TSSOP56  
HVQFN56  
OE  
30  
55  
56  
23  
48  
49  
I
active LOW output enable input  
active LOW interrupt output  
active LOW reset input  
INT  
O
I
RESET  
[1] HVQFN56 package die supply ground is connected to both VSS pins and exposed center pad. VSS pins  
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and  
board level performance, the exposed pad needs to be soldered to the board using a corresponding  
thermal pad on the board and for proper heat conduction through the board, thermal vias need to be  
incorporated in the printed-circuit board in the thermal pad region.  
7. Functional description  
Refer to Figure 1 “Block diagram of PCA9505/06” and Figure 2 “Simplified schematic of  
IO0_0 to IO4_7”.  
7.1 Device address  
Following a START condition, the bus master must send the address of the slave it is  
accessing and the operation it wants to perform (read or write). The address of the  
PCA9505/06 is shown in Figure 5. Slave address pins A2, A1, and A0 choose 1 of 8 slave  
addresses and need to be connected to VDD (1) or VSS (0). To conserve power, no internal  
pull-up resistors are incorporated on A2, A1, and A0.  
slave address  
0
1
0
0
A2 A1 A0 R/W  
fixed  
programmable  
002aab494  
Fig 5. PCA9505/06 address  
The last bit of the first byte defines the operation to be performed. When set to logic 1 a  
read is selected, while a logic 0 selects a write operation.  
7.2 Command register  
Following the successful acknowledgement of the slave address + R/W bit, the bus  
master will send a byte to the PCA9505/06, which will be stored in the Command register.  
AI  
1
D5 D4 D3 D2 D1 D0  
default at power-up  
or after RESET  
0
0
0
0
0
0
0
register number  
002aab495  
Auto-Increment  
Fig 6. Command register  
PCA9505_9506  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 4 — 3 August 2010  
7 of 34  
 
 
 
 

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