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PCA9506DGG,512

更新时间： 2024-01-13 10:21:56
品牌 Logo 应用领域
恩智浦 - NXP PC光电二极管外围集成电路
页数 文件大小 规格书
34页 264K
描述
PCA9505/06 - 40-bit I2C-bus I/O port with RESET, OE and INT TSSOP 56-Pin

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PCA9506DGG,512 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP56,.3,20
针数：56Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：7.94
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：14 mm湿度敏感等级：3
位数：40I/O 线路数量：8
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：2.5/5 V认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Parallel IO Port
最大供电电压：5.5 V最小供电电压：2.3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：6.1 mm
uPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches：1

PCA9506DGG,512 数据手册

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PCA9505/06  
NXP Semiconductors  
40-bit I2C-bus I/O port with RESET, OE and INT  
The lowest 6 bits are used as a pointer to determine which register will be accessed. The  
registers are:  
• IP: Input Port registers (5 registers)  
• OP: Output Port registers (5 registers)  
• PI: Polarity Inversion registers (5 registers)  
• IOC: I/O Configuration registers (5 registers)  
• MSK: Mask interrupt registers (5 registers)  
If the Auto-Increment flag is set (AI = 1), the 3 least significant bits are automatically  
incremented after a read or write. This allows the user to program and/or read the  
5 register banks sequentially.  
If more than 5 bytes of data are written and AI = 1, previous data in the selected registers  
will be overwritten. Reserved registers are skipped and not accessed (refer to Table 3).  
If the Auto-Increment flag is cleared (AI = 0), the 3 least significant bits are not  
incremented after data is read or written. During a read operation, the same register bank  
is read each time. During a write operation, data is written to the same register bank each  
time.  
Only a Command register code with the 5 least significant bits equal to the 25 allowable  
values as defined in Table 3 are valid. Reserved or undefined command codes must not  
be accessed for proper device functionality. At power-up, this register defaults to 0x80,  
with the AI bit set to logic 1, and the lowest 7 bits set to logic 0.  
During a write operation, the PCA9505/06 will acknowledge a byte sent to OPx, PIx, and  
IOCx and MSKx registers, but will not acknowledge a byte sent to the IPx registers since  
these are read-only registers.  
PCA9505_9506  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 4 — 3 August 2010  
8 of 34  
1...567891011...34

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PCA9506DGG,512 替代型号

型号 品牌 替代类型 描述 数据表
PCA9505DGG,112 NXP

类似代替

 		PCA9505/06 - 40-bit I2C-bus I/O port with RESET, OE and INT TSSOP 56-Pin
PCA9505DGG NXP

功能相似

 		40-bit I2C-bus I/O port with RESET, OE and INT

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