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PCA9500PW PDF预览

PCA9500PW

更新时间: 2024-02-11 01:58:14
品牌 Logo 应用领域
恩智浦 - NXP 并行IO端口微控制器和处理器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
23页 169K
描述
8-bit I2C and SMBus I/O port with 2-kbit EEPROM

PCA9500PW 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:TSSOP, TSSOP16,.25Reach Compliance Code:unknown
风险等级:5.78Is Samacsys:N
JESD-30 代码:R-PDSO-G16位数:8
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3/3.3 V认证状态:Not Qualified
子类别:Parallel IO Port表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUALBase Number Matches:1

PCA9500PW 数据手册

 浏览型号PCA9500PW的Datasheet PDF文件第1页浏览型号PCA9500PW的Datasheet PDF文件第2页浏览型号PCA9500PW的Datasheet PDF文件第3页浏览型号PCA9500PW的Datasheet PDF文件第5页浏览型号PCA9500PW的Datasheet PDF文件第6页浏览型号PCA9500PW的Datasheet PDF文件第7页 
Philips Semiconductors  
Product data sheet  
8-bit I2C and SMBus I/O port with 2-kbit EEPROM  
PCA9500  
FUNCTIONAL DESCRIPTION  
V
DD  
WRITE PULSE  
100 µA  
DATA FROM  
SHIFT REGISTER  
D
C
Q
FF  
I/O0 TO I/O7  
I
S
POWER-ON  
RESET  
V
SS  
D
C
Q
FF  
I
READ PULSE  
S
DATA TO  
SHIFT REGISTER  
SW00546  
Figure 4. Simplified schematic diagram of each I/O  
DEVICE ADDRESSING  
Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9500 is shown in  
Figure 5. Internal pullup resistors are incorporated on the hardware selectable address pins.  
SLAVE ADDRESS  
SLAVE ADDRESS  
R/W  
R/W  
0
1
0
0
A2 A1 A0  
HARDWARE  
1
0
1
0
A2 A1 A0  
FIXED  
FIXED  
HARDWARE  
PROGRAMMABLE  
PROGRAMMABLE  
(a) I/O EXPANDER  
(b) MEMORY  
a.  
b.  
SW01075  
Figure 5. PCA9500 slave addresses  
The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write  
operation.  
4
2004 Sep 30  

PCA9500PW 替代型号

型号 品牌 替代类型 描述 数据表
PCA9500PW,118 NXP

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