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PCA8550DBRE4

更新时间： 2024-11-09 04:11:03
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
12页 209K
描述
NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE

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PCA8550DBRE4 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SSOP, SSOP16,.3针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.37系列：8550
JESD-30 代码：R-PDSO-G16长度：6.2 mm
负载电容（CL）：15 pF逻辑集成电路类型：MULTIPLEXER
最大I（ol）：0.006 A功能数量：1
输入次数：4输出次数：1
端子数量：16最高工作温度：70 °C
最低工作温度：输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP16,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TAPE AND REEL
电源：3.3 VProp。Delay @ Nom-Sup：20 ns
传播延迟（tpd）：20 ns认证状态：Not Qualified
座面最大高度：2 mm子类别：Multiplexer/Demultiplexers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：5.3 mm
Base Number Matches：1

PCA8550DBRE4 数据手册

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PCA8550  
NONVOLATILE 5-BIT REGISTER  
WITH I2C INTERFACE  
www.ti.com  
SCPS050C–MARCH 1999–REVISED MAY 2005  
FEATURES  
D, DB, OR PW PACKAGE  
(TOP VIEW)  
•
EPIC™ (Enhanced-Performance Implanted  
CMOS) Submicron Process  
2
I C SCL  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
•
Useful for Jumperless Configuration of PC  
Motherboard  
2
I C SDA  
WP  
OVERRIDE  
MUX IN A  
MUX IN B  
MUX IN C  
MUX IN D  
GND  
NON-MUXED OUT  
MUX SELECT  
•
•
•
•
•
•
Inputs Accept Voltages to 5.5 V  
MUX OUT Signals are 2.5-V Outputs  
NON-MUXED OUT Signal is a 3.3-V Output  
Minimum of 1000 Write Cycles  
12 MUX OUT A  
11  
10  
9
MUX OUT B  
MUX OUT C  
MUX OUT D  
Minimum of 10 Years Data Retention  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline (DB),  
and Thin Shrink Small-Outline (PW) Packages  
DESCRIPTION/ORDERING INFORMATION  
This 4-bit 1-of-2 multiplexer with I2C input interface is designed for 3-V to 3.6-V VCC operation.  
The PCA8550 is designed to multiplex four bits of data from parallel inputs or from I2C input data stored in a  
nonvolatile register. An additional bit of register output also is provided, which is latched to prevent changes in  
the output value during the write cycle. The factory default for the contents of the register is all low. These stored  
values can be read from, or written to, using the I2C bus. The ability to control writing to the register is provided  
by the write protect (WP) input. The override (OVERRIDE) input forces all the register outputs to a low.  
This device provides a fast-mode (400 kbit/s) or standard-mode (100 kbit/s) I2C serial interface for data input and  
output. The implementation is as a slave. The device address is specified in the I2C interface definition table.  
Both of the I2C Schmitt-trigger inputs (SCL and SDA) provide integrated pullup resistors and are 5-V tolerant.  
The PCA8550 requires a monotonic power-supply ramp at start-up in the region of 1.1 V to 2.5 V. The  
nonvolatile registers and I2C state machine initialize to their default states after this VCC level is passed.  
The PCA8550 is characterized for operation from 0°C to 70°C.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
PCA8550D  
TOP-SIDE MARKING  
Tube of 40  
SOIC – D  
Reel of 2500  
Reel of 2000  
Reel of 2000  
PCA8550DR  
PCA8550DBR  
PCA8550PWR  
0°C to 70°C  
PCA8550  
SSOP – DB  
TSSOP – PW  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...12

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