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PC87200VUL

更新时间： 2024-01-26 11:58:55
品牌 Logo 应用领域
华邦 - WINBOND 时钟PC外围集成电路
页数 文件大小 规格书
33页 426K
描述
ISA Bus Controller, CMOS, PQFP160, PLASTIC, QFP-160

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PC87200VUL 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：QFP,
针数：160Reach Compliance Code：not_compliant
ECCN代码：3A991.A.2HTS代码：8542.31.00.01
风险等级：5.81地址总线宽度：32
总线兼容性：PCI最大时钟频率：33.33 MHz
外部数据总线宽度：32JESD-30 代码：S-PQFP-G160
JESD-609代码：e0长度：28 mm
湿度敏感等级：2A端子数量：160
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装形状：SQUARE封装形式：FLATPACK
峰值回流温度（摄氏度）：220认证状态：Not Qualified
座面最大高度：4.1 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：28 mmuPs/uCs/外围集成电路类型：BUS CONTROLLER, ISA
Base Number Matches：1

PC87200VUL 数据手册

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3.0 Device Overview (Continued)  
When a legacy ISA bus DMA request is asserted, the 3.5.1 Clock Generation  
PC87200 will transmit that request to the PC/PCI Primary  
The PC87200 generates the ISA clock using PCI clock sig-  
Bus Arbiter by encoding it and driving it out the PC87200’s  
PCPCIREQ# according to the above; first PCPCIREQ# will  
be driven low for one PCICLK period to indicate that the  
serial encoded request transfer is starting. Then the  
PC87200 will drive each of the next eight bits with the value  
of its corresponding DREQ. (NOTE: Channel 4 will always  
be driven low.) At the end of the request sequence, the  
PC87200 will continue to drive its PCPCIREQ# signal  
active, indicating that the request is still being maintained.  
nal (typically 33 MHz).  
A PCICLK divisor (3,4) is programmable through PCI con-  
figuration register to generate the ISA clock signal. This  
provides support for the generation of ISACLK frequencies  
8.33 MHz and 11 MHz off of a 33MHz PCICLK.  
Figure 3. shows a block diagram for clock generation within  
the PC87200.  
In response to the request sequence, the PC/PCI Primary  
Bus Arbiter will respond with a PC/PCI DMA encoded grant  
transfer when it is granting the PCI bus for a PC/PCI DMA  
transfer cycle. The PC/PCI encoded grant transfer will  
begin when the PC/PCI Primary Bus Arbiter drives  
PCPCIGNT# low for one PCICLK period to indicate the  
start of the grant sequence; then the next three  
PCPCIGNT# signal PCICLK periods will then contain the  
encoded grant value, indicating which legacy ISA DMA  
channel is being granted the PC Bus.  
PC87200  
N
PCICLK  
SYSCLK  
bit 2  
bit 1  
bit 0  
Channel Granted  
DMA Channel 0 (DACK0#)  
DMA Channel 0 (DACK1#)  
DMA Channel 0 (DACK2#)  
DMA Channel 0 (DACK3#)  
RESERVED  
Figure 3. PC87200 Clock Generation  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DMA Channel 0 (DACK5#)  
DMA Channel 0 (DACK6#)  
DMA Channel 0 (DACK7#)  
After receiving a valid grant from the PC/PCI DMA Arbiter,  
the PC87200 will recognize the following I/O accesses as  
DMA I/O Reads(Writes) from (to) the granted legacy ISA  
DMA channel.  
DMA Cycle  
Type  
DMA  
I/O Address  
TC (A2) PCI Cycle Type  
Normal  
0000_0000h  
0000_0004h  
0000_00C0h  
0000_00C4h  
0
1
0
1
I/O Read/Write  
I/O Read/Write  
I/O Read  
Normal TC  
Verify  
Verify TC  
I/O Read.  
PCI bus address bit 2 (A2) indicates if the cycle is to be a  
Terminal Count cycle or not.  
For Normal DMA Cycles, PCI bus I/O Reads and Writes  
will be translated to legacy ISA DMA Reads and Writes  
respectively. For Verify DMA Cycles, only PCI bus I/O  
Reads will be translated to legacy ISA DMA Verify cycles.  
www.national.com  
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