August 1990
PC87310 (SuperI/OTM)
Dual UART with Floppy Disk Controller
²
and Parallel Port
Y
Y
Decoding and chip selects for an IDE hard disk
interface
General Description
The PC87310 incorporates two full function UARTs, a flop-
py disk controller (FDC) with analog data separator, one
parallel port, game port decode, hard disk controller de-
code, standard XT/AT address decoding for on-chip func-
tions, and a Configuration Register in one chip. Thus it of-
fers a single chip solution to the most commonly used
Address decoding and strobe generation for a game
port
Y
Y
Y
Y
Fabricated in NSC’s 1.5 m M2CMOS process
Low power CMOS with a power down mode
100-pin EIAJ plastic flatpak package
Integrates all PC-XT , PC-AT logic
É
É
IBM PC, XT, and AT peripherals. The floppy disk controller
É
Ð On chip 24 MHz crystal oscillator
Ð DMA enable logic
is fully compatible with the industry standard 765 architec-
ture, but it includes many more advanced options such as a
high performance data separator, extended track range to
4096, implied seek command, scan command, and both
Ð IBM compatible address decode of A0–A9
Ð 24 mA mP bus interface buffers
Ð 40 mA floppy drive interface buffers
Ð Data rate and drive control registers
Precision analog data separator
Ð Self-calibrating PLL and delay line
Ð Automatically chooses one of three filters
Ð Intelligent read algorithm
standard IBM formats as well as ISO 3.5 formats. The
×
UARTs are compatible with either the INS8250N-B or the
NS16450. The parallel port, hard disk select, and game port
select logic maintain complete compatibility with the IBM XT
and AT. Hardware selects XT or AT compatibility.
Y
The Configuration Register is one byte wide and can be
programmed via hardware or software. Through its control,
the user can assign standard AT addresses and disable any
major on-chip function (e.g., the FDC, either UART, or the
parallel port) independently of the others. This allows for
flexibility in system configuration when adapter cards con-
tain duplicate functions.
Y
Y
Two pin programmable precompensation modes
Other enhancements
Ð Implied seek up to 4000 tracks
Ð IBM or ISO formatting
Y
Y
Y
Y
Separate interrupt request lines for the parallel and se-
rial ports
Adds or deletes standard asynchronous communication
bits (start, parity, and stop) to or from the serial data
Independently controlled transmit, receive, line status,
and data set interrupts
Features
Y
100% compatible to the IBM PC, XT and AT
architectures
Y
Software compatible to the INS8250N-B, INS8250A and
NS16450 UARTs
Programmable baud generators for each UART channel
16
b
divide the input clock by 1 to (2
c
1) and generate
Y
the internal 16
sample clock
100% compatible to the industry standard 765A
architecture
Y
Y
MODEM control functions for each UART channel
(CTS, RTS, DSR, DTR, RI and DCD)
Y
On-chip analog data separator operates up to 1 Mb/s
Y
Fully programmable serial-interface characteristics:
Ð 5, 6, 7, or 8 bit characters
Ð Even, odd, or no parity generation and detection
Ð 1, 1(/2, or 2 stop bit generation
Implements all DP8473 Floppy Disk Controller functions
Y
Bidirectional parallel port for printer or scanner opera-
tion. Provides all standard Centronics and IBM PC, XT,
and AT interface signals.
Y
High current drive capability for the parallel port
Note: This part is patented.
²
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
Plus-2TM and SuperI/OTM are trademarks of National Semiconductor Corporation.
IBMÉ, PC-XTÉ, PC-ATÉ and PS/2É are registered trademarks of International Business Machines Corporation.
C
1995 National Semiconductor Corporation
TL/C/10591
RRD-B30M65/Printed in U. S. A.