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PC16550DV PDF预览

PC16550DV

更新时间: 2024-02-05 09:04:46
品牌 Logo 应用领域
美国国家半导体 - NSC 先进先出芯片PC
页数 文件大小 规格书
22页 345K
描述
PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs

PC16550DV 技术参数

生命周期:Obsolete包装说明:DIE, DIE OR CHIP
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.75地址总线宽度:3
边界扫描:NO总线兼容性:8088
最大时钟频率:24 MHz通信协议:ASYNC, BIT
最大数据传输速率:0.1875 MBps外部数据总线宽度:8
JESD-30 代码:X-XUUC-N低功率模式:NO
串行 I/O 数:1最高工作温度:70 °C
最低工作温度:封装主体材料:UNSPECIFIED
封装代码:DIE封装等效代码:DIE OR CHIP
封装形状:UNSPECIFIED封装形式:UNCASED CHIP
电源:5 V认证状态:Not Qualified
子类别:Serial IO/Communication Controllers最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子位置:UPPERuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches:1

PC16550DV 数据手册

 浏览型号PC16550DV的Datasheet PDF文件第2页浏览型号PC16550DV的Datasheet PDF文件第3页浏览型号PC16550DV的Datasheet PDF文件第4页浏览型号PC16550DV的Datasheet PDF文件第6页浏览型号PC16550DV的Datasheet PDF文件第7页浏览型号PC16550DV的Datasheet PDF文件第8页 
3.0 AC Electrical Characteristics (Continued)  
Symbol  
Parameter  
Conditions  
Min  
Max  
Units  
Transmitter  
t
t
t
t
t
t
t
Delay from WR, WR (WR THR)  
to Reset Interrupt  
100 pF Load  
100 pF Load  
HR  
175  
250  
24  
ns  
ns  
Delay from RD, RD (RD IIR) to Reset  
Interrupt (THRE)  
IR  
Delay from Initial INTR Reset to Transmit  
Start  
BAUDOUT  
Cycles  
IRS  
SI  
8
16  
8
Delay from Initial Write to Interrupt  
Delay from Stop to Interrupt (THRE)  
Delay from Start to TXRDY active  
Delay from Write to TXRDY inactive  
(Note 1)  
(Note 1)  
BAUDOUT  
Cycles  
24  
BAUDOUT  
Cycles  
STI  
SXA  
WXI  
8
100 pF Load  
100 pF Load  
BAUDOUT  
Cycles  
8
195  
ns  
Modem Control  
t
t
t
Delay from WR, WR (WR MCR) to  
Output  
100 pF Load  
100 pF Load  
100 pF Load  
MDO  
RIM  
SIM  
200  
ns  
Delay from RD, RD to Reset Interrupt  
(RD MSR)  
250  
250  
ns  
ns  
Delay from MODEM Input to Set Interrupt  
Note 1: This delay will be lengthened by 1 character time, minus the last stop bit time if the transmitter interrupt delay circuit is active. (See FIFO Interrupt Mode  
Operation).  
Note 2: These specifications are preliminary.  
4.0 Timing Waveforms (All timings are referenced to valid 0 and valid 1)  
External Clock Input (24.0 MHz Max.)  
AC Test Points  
TL/C/8652–3  
TL/C/8652–2  
Note 1: The 2.4V and 0.4V levels are the voltages that the inputs are driven to during AC testing.  
Note 2: The 2.0V and 0.8V levels are the voltages at which the timing tests are made.  
BAUDOUT Timing  
TL/C/8652–4  
5

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