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PAS302BCW-22S PDF预览

PAS302BCW-22S

更新时间: 2024-10-28 05:59:35
品牌 Logo 应用领域
原相 - PIXART 传感器图像传感器
页数 文件大小 规格书
15页 237K
描述
CMOS VGA DIGITAL IMAGE SENSOR

PAS302BCW-22S 数据手册

 浏览型号PAS302BCW-22S的Datasheet PDF文件第5页浏览型号PAS302BCW-22S的Datasheet PDF文件第6页浏览型号PAS302BCW-22S的Datasheet PDF文件第7页浏览型号PAS302BCW-22S的Datasheet PDF文件第9页浏览型号PAS302BCW-22S的Datasheet PDF文件第10页浏览型号PAS302BCW-22S的Datasheet PDF文件第11页 
PAS302BCW-22S  
CMOS Image Sensor IC  
5.2Data Transfer Format  
5.2.1 Master transmits data to slave (write cycle)  
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S : Start  
A : Acknowledge by slave  
P : Stop  
RW : The LSB of 1st byte to decide whether current cycle is read or write cycle.  
If RW=1 that means read cycle, if RW=0 that means write cycle.  
ƒ
SUBADDRESS : The address values of PAS302BCW-22S internal control registers  
(Please refer to PAS302BCW-22S register description)  
1ST BYTE  
2ND BYTE  
n BYTEs + A  
S
SLAVE ID (7 BIT)  
RW  
A
SUBADDRESS (8 BIT)  
A
DATA  
A
DATA  
A
P
MSB  
LSB=0  
During the write cycle, the master generates start condition and then places the 1st byte data  
that combined slave address (7 bits) with a read/write control bit on SDA line. After  
slave(PAS302BCW-22S) issues acknowledgment, the master places 2nd byte (sub-address)  
data on SDA line. And then following the slave’s( PAS302BCW-22S) acknowledgment, the  
master places the 8 bits data on SDA line and transmit to PAS302BCW-22S control register  
(address was assigned by 2nd byte). After PAS302BCW-22S issue acknowledgment, the  
master can generate a stop condition to end this write cycle. In the condition of multi-byte write,  
the PAS302BCW-22S sub-address will be increased automatically after each DATA byte has  
been transferred. The Data and A cycles are repeated until last byte write. Every control  
registers value inside PAS302BCW-22S can be programming via this way. (Please refer to  
Figure 5.3.)  
5.2.2 Slave transmits data to master (read cycle)  
ƒ The sub-address was assigned by previous write cycle  
ƒ The sub-address is automatically increased after each byte read  
ƒ Am : Acknowledged by master  
ƒ Note: there is no acknowledgment from master after last byte read  
1ST BYTE  
2ND BYTE  
n BYTE  
Am  
SLAVE ADDRESS  
(7 BITS)  
S
RW  
A
DATA (8 BIT)  
Am DATA  
DATA  
1
P
NO ACK IN LAST  
BYTE  
During read cycle, the master generates start condition and then place the 1st byte data that  
combine slave address (7 bits) with a read/write control bit to SDA line. After slave issue  
acknowledgment, 8 bits DATA was placed on SDA line by PAS302BCW-22S. The 8 bit data was  
read from PAS302BCW-22S internal control register that address was assigned by previous  
write cycle. Following the master acknowledgment, the PAS302BCW-22S place the next 8 bits  
data (address is increased automatically) on SDA line and then transfer to master serially. The  
Version 2.4, 20 Sep. 2005  
PixArt Imaging Inc.  
8
E-mail: fae_service@pixart.com.tw  

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