PAS302BCA-32
CMOS Image Sensor IC
generated by master but instead of keeping SDA line as high. The slave (PAS302BCA-32) must
releases SDA line back to master to generate STOP condition. (Please refer to Figure 5.3.)
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
P
S
ACK
from
Receiver
ACK
from
Receiver
Stop
Condition
ACK
from
Receiver
Address
R/W
Data
Data
Start
Condition
Figure 5.3 Data Transfer Format
5.3. I2CTM Bus Timing
SDA
t
BUF
t
HD;STA
tr
t
f
t
SP
t
f
t
r
tSU;DAT
t
LOW
SCL
t
SU;STO
P
S
S
Sr
t
HD;STA
t
SU;STA
t
HD;DAT
t
HIGH
Figure 5.4 I2CTM Bus Timing
5.4. I2CTM Bus Timing Specification
STANDARD-MODE
UNIT
PARAMETER
SYMBOL
MIN.
MAX.
SCL clock frequency
10
400
kHz
µs
f
t
scl
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
4.0
-
HD:STA
Low period of the SCL clock
4.7
0.75
4.7
-
µs
µs
µs
µs
ns
ns
ns
µs
µs
pF
V
t
t
t
t
t
t
t
t
t
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
r
HIGH period of the SCL clock
-
Set-up time for a repeated START condition
-
3.45
-
Data hold time. For I2CTM bus device
0
Data set-up time
250
30
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
N.D.(Note)
30
N.D. (Note)
f
4.0
-
-
SU;STO
BUF
Bus free time between a STOP and START
Capacitive load for each bus line
4.7
1
15
-
C
V
b
Noise margin at LOW level for each
connected device (including hysteresis)
0.1 VDD
nL
Version 2.3, 13 Sep. 2004
PixArt Imaging Inc.
10
E-mail: fae_service@pixart.com.tw