Datasheet > PALCE20V8H-5JI5

PALCE20V8H-5JI5

更新时间： 2024-09-20 23:02:55

品牌	Logo	应用领域
超微 - AMD		/
页数	文件大小	规格书
16页	169K
描述
EE CMOS 24-Pin Universal Programmable Array Logic

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中文翻译

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数据手册

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PALCE20V8H-5JI5 数据手册

FINAL

COM’L: H-5/7/10/15/25, Q-10/15/25

IND: H-15/25, Q-20/25

Advanced

Micro

PALCE20V8 Family

EE CMOS 24-Pin Universal Programmable Array Logic

Devices

DISTINCTIVE CHARACTERISTICS

■ Pin and function compatible with all GAL

20V8/As

■ Peripheral Component Interconnect (PCI)

compliant

■ Electrically erasable CMOS technology pro-

vides reconfigurable logic and full testability

■ High-speed CMOS technology

— 5-ns propagation delay for “-5” version

■ Preloadable output registers for testability

■ Automatic register reset on power-up

■ Cost-effective 24-pin plastic SKINNYDIP and

28-pin PLCC packages

■ Extensive third-party software and programmer

support through FusionPLD partners

■ Fully tested for 100% programming and func-

tional yields and high reliability

■ Programmable output polarity

■ 5-ns version utilizes a split leadframe for

improved performance

— 7.5-ns propagation delay for “-7” version

■ Direct plug-in replacement for a wide range of

24-pin PAL devices

■ Programmable enable/disable control

■ Outputs individually programmable as

registered or combinatorial

GENERAL DESCRIPTION

The PALCE20V8 is an advanced PAL device built with

low-power, high-speed, electrically-erasable CMOS

technology. Its macrocells provide a universal device

architecture. The PALCE20V8 is fully compatible with

the GAL20V8 and can directly replace PAL20R8 series

devices and most 24-pin combinatorial PAL devices.

complex logic functions easily and efficiently. Multiple

levels of combinatorial logic can always be reduced to

sum-of-products form, taking advantage of the very

wide input gates available in PAL devices. The equa-

tions are programmed into the device through floating-

gate cells in the AND logic array that can be erased

electrically.

Devicelogicisautomaticallyconfiguredaccordingtothe

user’s design specification. A design is implemented

using any of a number of popular design software pack-

ages, allowing automatic creation of a programming file

based on Boolean or state equations. Design software

also verifies the design and can provide test vectors for

the finished device. Programming can be accomplished

on standard PAL device programmers.

The fixed OR array allows up to eight data product terms

per output for logic functions. The sum ofthese products

feeds the output macrocell. Each macrocell can be

programmed as registered or combinatorial with an

active-high or active-low output. The output configura-

tion is determined by two global bits and one local bit

controlling four multiplexers in each macrocell.

The PALCE20V8 utilizes the familiar sum-of-products

(AND/OR) architecture that allows users to implement

I₁– I₁₀

CLK/I₀

BLOCK DIAGRAM

Programmable AND Array

40 x 64

Input

Mux.

Input

Mux.

MACRO

MC₀

MACRO

MC₁

MACRO

MC₂

MACRO

MC₃

MACRO

MC₄

MACRO

MC₅

MACRO

MC₆

MACRO

MC₇

I/O₆

OE/I₁₁I₁₂

I/O₀

I/O₁

I/O₂

I/O₄

I/O₇

I₁₃

I/O₅

16491D-1

Publication# 16491 Rev. D Amendment/0

Issue Date: February 1996

2-155

12 3 4 5 6 7...16

中文翻译

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与PALCE20V8H-5JI5相关器件

型号	品牌	获取价格	描述	数据表
PALCE20V8H-5PC	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8H-5PC4	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8H-5PC5	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8H-5PI	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8H-5PI4	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8H-5PI5	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8H-7JC	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8H-7JC/5	LATTICE	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8H-7JC/5	ROCHESTER	获取价格	EE PLD, 7.5 ns, PQCC28, PLASTIC, LCC-28
PALCE20V8H-7JC4	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic

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