5秒后页面跳转
PAL16L8DDC PDF预览

PAL16L8DDC

更新时间: 2024-11-24 03:11:27
品牌 Logo 应用领域
超微 - AMD /
页数 文件大小 规格书
33页 218K
描述
20-Pin TTL Programmable Array Logic

PAL16L8DDC 数据手册

 浏览型号PAL16L8DDC的Datasheet PDF文件第2页浏览型号PAL16L8DDC的Datasheet PDF文件第3页浏览型号PAL16L8DDC的Datasheet PDF文件第4页浏览型号PAL16L8DDC的Datasheet PDF文件第5页浏览型号PAL16L8DDC的Datasheet PDF文件第6页浏览型号PAL16L8DDC的Datasheet PDF文件第7页 
FINAL  
COM’L: -4/5/7/B/B-2/A, D/2  
Advanced  
Micro  
PAL16R8 Family  
20-Pin TTL Programmable Array Logic  
Devices  
DISTINCTIVE CHARACTERISTICS  
As fast as 4.5 ns maximum propagation delay  
Power-up reset for initialization  
Popular 20-pin architectures: 16L8, 16R8, 16R6,  
Extensive third-party software and programmer  
16R4  
support through FusionPLD partners  
Programmable replacement for high-speed TTL  
20-Pin DIP and PLCC packages save space  
logic  
28-Pin PLCC-4 package provides ultra-clean  
Register preload for testability  
high-speed signals  
GENERAL DESCRIPTION  
The PAL16R8 Family (PAL16L8, PAL16R8, PAL16R6,  
PAL16R4) includes the PAL16R8-5/4 Series which pro-  
vides the highest speed in the 20-pin TTL PAL device  
family, making the series ideal for high-performance ap-  
plications. The PAL16R8 Family is provided with stan-  
dard 20-pin DIP and PLCC pinouts and a 28-pin PLCC  
pinout. The 28-pin PLCC pinout contains seven extra  
ground pins interleaved between the outputs to reduce  
noise and increase speed.  
The AND array is programmed to create custom product  
terms, while the OR array sums selected terms at the  
outputs.  
In addition, the PAL device provides the following  
options:  
— Variable input/output pin ratio  
— Programmable three-state outputs  
— Registers with feedback  
The devices provide user-programmable logic for re-  
placing conventional SSI/MSI gates and flip-flops at a  
reduced chip count.  
Product terms with all connections opened assume the  
logicalHIGHstate;producttermsconnectedtobothtrue  
and complement of any single input assume the logical  
LOW state. Registers consist of D-type flip-flops that are  
loaded on the LOW-to-HIGH transition of the clock. Un-  
used input pins should be tied to VCC or GND.  
The family allows the systems engineer to implement  
the design on-chip, by opening fuse links to configure  
AND and OR gates within the device, according to the  
desired logic function. Complex interconnections be-  
tween gates, which previously required time-consuming  
layout, are lifted from the PC board and placed on sili-  
con, where they can be easily modified during proto-  
typing or production.  
The entire PAL device family is supported by the  
FusionPLD partners. The PAL family is programmed on  
conventionalPALdeviceprogrammerswithappropriate  
personality and socket adapter modules. Once the PAL  
device is programmed and verified, an additional con-  
nection may be opened to prevent pattern readout. This  
feature secures proprietary circuits.  
The PAL device implements the familiar Boolean logic  
transfer function, the sum of products. The PAL device  
is a programmable AND array driving a fixed OR array.  
PRODUCT SELECTOR GUIDE  
Dedicated  
Product Terms/  
Device  
Inputs  
Outputs  
Output  
Feedback  
Enable  
PAL16L8  
10  
6 comb.  
2 comb.  
7
7
I/O  
prog.  
prog.  
PAL16R8  
PAL16R6  
8
8
8 reg.  
8
reg.  
pin  
6 reg.  
2 comb.  
8
7
reg.  
I/O  
pin  
prog.  
PAL16R4  
8
4 reg.  
4 comb.  
8
7
reg.  
I/O  
pin  
prog.  
Publication# 16492 Rev. D Amendment/0  
Issue Date: February 1996  
2-3  

与PAL16L8DDC相关器件

型号 品牌 获取价格 描述 数据表
PAL16L8DJC AMD

获取价格

20-Pin TTL Programmable Array Logic
PAL16L8DMJ/883B ETC

获取价格

Fuse-Programmable PLD
PAL16L8DML/883B ETC

获取价格

Fuse-Programmable PLD
PAL16L8DMW/883B ETC

获取价格

Fuse-Programmable PLD
PAL16L8DNC ROCHESTER

获取价格

OT PLD, 10ns, TTL, PDIP20, PLASTIC, DIP-20
PAL16L8DNC TI

获取价格

OT PLD, 10ns, PDIP20, PLASTIC, DIP-20
PAL16L8DPC AMD

获取价格

20-Pin TTL Programmable Array Logic
PAL16L8DVC ETC

获取价格

Fuse-Programmable PLD
PAL16L8H-15DC ETC

获取价格

Fuse-Programmable PLD
PAL16L8H-15JC ETC

获取价格

Fuse-Programmable PLD