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P4C1256-55L32MLF PDF预览

P4C1256-55L32MLF

更新时间: 2024-11-12 15:47:19
品牌 Logo 应用领域
PYRAMID 静态存储器内存集成电路
页数 文件大小 规格书
16页 1155K
描述
Standard SRAM, 32KX8, 55ns, CMOS, 0.450 X 0.550 INCH, ROHS COMPLIANT, LCC-32

P4C1256-55L32MLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFJ
包装说明:QCCN,针数:32
Reach Compliance Code:compliantECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.56
最长访问时间:55 nsJESD-30 代码:R-XQCC-N32
长度:13.97 mm内存密度:262144 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1端子数量:32
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:32KX8
封装主体材料:UNSPECIFIED封装代码:QCCN
封装形状:RECTANGULAR封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified筛选级别:MIL-STD-883
座面最大高度:1.905 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:11.43 mm
Base Number Matches:1

P4C1256-55L32MLF 数据手册

 浏览型号P4C1256-55L32MLF的Datasheet PDF文件第2页浏览型号P4C1256-55L32MLF的Datasheet PDF文件第3页浏览型号P4C1256-55L32MLF的Datasheet PDF文件第4页浏览型号P4C1256-55L32MLF的Datasheet PDF文件第5页浏览型号P4C1256-55L32MLF的Datasheet PDF文件第6页浏览型号P4C1256-55L32MLF的Datasheet PDF文件第7页 
P4C1256  
HIGH SPEED 32K x 8  
STATIC CMOS RAM  
FEATURES  
High Speed (Equal Access and Cycle Times)  
– 12/15/20/25/35 ns (Commercial)  
– 15/20/25/35/45 ns (Industrial)  
– 20/25/35/45/55/70 ns (Military)  
Low Power  
Single 5V±10% Power Supply  
Easy Memory Expansion Using CE and OE Inputs  
Common Data I/O  
Fast tOE  
Automatic Power Down  
Packages  
– 28-Pin 300 mil DIP, SOJ, TSOP  
– 28-Pin 300 mil Ceramic DIP  
– 28-Pin 600 mil Plastic and Ceramic DIP  
– 28-Pin CERPACK  
– 28-Pin Solder Seal Flat Pack  
– 28-Pin SOP  
Three-State Outputs  
Fully TTL Compatible Inputs and Outputs  
Advanced CMOS Technology  
– 28-Pin LCC (350 mil x 550 mil)  
– 32-Pin LCC (450 mil x 550 mil)  
DESCRIPTIOꢀ  
The P4C1256 is a 262,144-bit high-speed CMOS static  
RAM organized as 32K x 8. The CMOS memory requires  
no clocks or refreshing, and has equal access and cycle  
times. InputsarefullyTTL-compatible. TheRAMoperates  
from a single 5V±10% tolerance power supply.  
with matching access and cycle times. Memory locations  
are specified on address pinsA0 toA14. Reading is accom-  
plished by device selection (CE) and output enabling (OE)  
while write enable (WE) remains HIGH. By presenting the  
address under these conditions, the data in the addressed  
memorylocationispresentedonthedatainput/outputpins.  
The input/output pins stay in the HIGH Z state when either  
CE or OE is HIGH or WE is LOW.  
Access times as fast as 12 nanoseconds permit greatly  
enhanced system operating speeds. CMOS is utilized to  
reduce power consumption to a low level. The P4C1256  
is a member of a family of PACE RAM™ products offering  
fast access times.  
PackageoptionsfortheP4C1256include28-pinDIP,SOJ,  
and TSOP packages. For military temperature range,  
Ceramic DIP and LCC packages are available.  
The P4C1256 devices provides asynchronous operation  
FUꢀCTIOꢀAL BLOCK DIAꢁRAM  
PIꢀ COꢀFIꢁURATIOꢀS  
DIP (P5, P6, C5, C5-1, D5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3)  
CERPACK (F4, FS-5) SIMILAR  
LCC and TSOP configurations at end of datasheet  
Document # SRAM119 REV I  
Revised July 2010  

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