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P4C1256-45DMB PDF预览

P4C1256-45DMB

更新时间: 2024-11-12 20:17:27
品牌 Logo 应用领域
PYRAMID 静态存储器内存集成电路
页数 文件大小 规格书
8页 90K
描述
Standard SRAM, 32KX8, 45ns, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28

P4C1256-45DMB 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:28
Reach Compliance Code:compliantECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5
Is Samacsys:N最长访问时间:45 ns
JESD-30 代码:R-CDIP-T28JESD-609代码:e0
内存密度:262144 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:28字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:32KX8封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
筛选级别:MIL-STD-883 Class B座面最大高度:5.8928 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15.24 mm
Base Number Matches:1

P4C1256-45DMB 数据手册

 浏览型号P4C1256-45DMB的Datasheet PDF文件第2页浏览型号P4C1256-45DMB的Datasheet PDF文件第3页浏览型号P4C1256-45DMB的Datasheet PDF文件第4页浏览型号P4C1256-45DMB的Datasheet PDF文件第5页浏览型号P4C1256-45DMB的Datasheet PDF文件第6页浏览型号P4C1256-45DMB的Datasheet PDF文件第7页 
P4C1256  
HIGH SPEED 32K x 8  
STATIC CMOS RAM  
FEATURES  
Three-State Outputs  
High Speed (Equal Access and Cycle Times)  
— 12/15/20/25/35 ns (Commercial)  
— 15/20/25/35/45 ns (Industrial)  
— 20/25/35/45/55/70 ns (Military)  
Low Power  
— 880 mW Active (Commercial)  
Single 5V±10% Power Supply  
Easy Memory Expansion Using CE and OE  
Inputs  
Fully TTL Compatible Inputs and Outputs  
Advanced CMOS Technology  
Fast tOE  
Automatic Power Down  
Packages  
—28-Pin 300 mil DIP and SOJ  
—28-Pin 600 mil Ceramic DIP  
—28-Pin LCC(350 mil x 550 mil)  
—32-Pin LCC (450 mil x 550 mil)  
Common Data I/O  
DESCRIPTION  
The P4C1256 is a 262,144-bit high-speed CMOS  
static RAM organized as 32Kx8. The CMOS memory  
requires no clocks or refreshing, and has equal access  
and cycle times. Inputs are fully TTL-compatible. The  
RAM operates from a single 5V±10% tolerance power  
supply.  
The P4C1256 device provides asynchronous operation with  
matching access and cycle times. Memory locations are  
specified on address pins A0 to A14. Reading is accom-  
plished by device selection (CE and output enabling (OE)  
while write enable (WE) remains HIGH. By presenting the  
address under these conditions, the data in the addressed  
memory location is presented on the data input/output pins.  
The input/output pins stay in the HIGH Z state when either  
CE or OE is HIGH or WE is LOW.  
Access times as fast as 12 nanoseconds permit greatly  
enhanced system operating speeds. CMOS is utilized  
to reduce power consumption to a low level. The  
P4C1256 is a member of a family of PACE RAM™ prod-  
ucts offering fast access times.  
Package options for the P4C1256 include 28-pin 300 mil  
DIP and SOJ packages. For military temperature range,  
Ceramic DIP and LCC packages are available.  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATIONS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
VCC  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
A
WE  
262,144-BIT  
MEMORY  
ARRAY  
(8)  
A
4
5
3
2
32  
31 30  
29  
3
A14  
A
A
A
A
A
A
A
A
A
A
1
13  
12  
11  
3
4
5
6
7
8
9
A13  
A12  
4
6
7
8
9
28  
27  
26  
25  
24  
5
A
11  
6
I/O  
NC  
1
7
OE  
INPUT  
DATA  
CONTROL  
OE  
A
A7  
A8  
A9  
A
10  
8
COLUMN I/O  
10  
11  
12  
13  
10  
9
CE  
I/O  
2
23  
22  
21  
CE  
I/O  
10  
11  
12  
13  
14  
I/0  
I/0  
I/0  
I/0  
I/0  
8
NC  
8
7
6
5
4
I/01  
I/O  
I/O  
1
7
I/02  
14 15 16 17 18 19 20  
COLUMN  
SELECT  
I/03  
GND  
WE  
CE  
OE  
• • • • • •  
DIP (P5, C5, D5-1), SOJ (J5)  
TOP VIEW  
32 LCC (L6)  
TOP VIEW  
A
(7)  
A
See Selection Guide page for 28-pin LCC  
Means Quality, Service and Speed  
1Q97  
117  

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