ORCA® ORT8850
Field-Programmable System Chip (FPSC)
Eight-Channel x 850 Mbits/s Backplane Transceiver
February 2008
Data Sheet
Introduction
Field Programmable System-on-a-Chip (FPSCs) bring a whole new dimension to programmable logic: Field Pro-
grammable Gate Array (FPGA) logic and an embedded system solution on a single device. Lattice has developed
a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high-
speed serial backplane data transfer. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC)
architecture, the ORT8850 family is made up of backplane transceivers (SERDES) containing eight channels, each
operating at up to 850 Mbits/s (6.8 Gbits/s when all eight channels are used). This is combined with a full-duplex
synchronous interface, with built-in Clock and Data Recovery (CDR) in standard-cell logic, along with over 600K
usable FPGA system gates (ORT8850H). With the addition of protocol and access logic such as protocol-indepen-
dent framers, Asynchronous Transfer Mode (ATM) framers, Packet-over-SONET (PoS) interfaces, and framers for
HDLC for Internet Protocol (IP), designers can build a configurable interface retaining proven backplane
driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within
a system that are not SONET/SDH based. For example, designers can build a 6.8 Gbits/s PCI-to-PCI half bridge
using our PCI soft core.
The ORT8850 family offers a clockless High-Speed Interface for inter-device communication on a board or across
a backplane. The built-in clock recovery of the ORT8850 allows for higher system performance, easier-to-design
clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefit from the
backplane transceiver as a network termination device. The backplane transceiver offers SONET scram-
bling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus
the programmable logic to terminate the network into proprietary systems. For non-SONET applications, all
SONET functionality is hidden from the user and no prior networking knowledge is required.
Table 1. ORCA ORT8850 Family – Available FPGA Logic (equivalent to OR4E02 and OR4E06 respectively)
FPGA
System
Gates (K)
PFU
FPGA Max
EBR
Blocks
EBR Bits
(K)
Device
PFU Rows Columns Total PFUs User I/Os
LUTs
4,992
ORT8850L
ORT8850H
26
46
24
44
624
278
297
8
74
201 - 397
471 - 899
2,024
16,192
16
148
Note: The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate
ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40%
EBR usage and 2 PLL's. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage
and 6 PLLs.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders.The specifications and information herein are subject to change without
notice.
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