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ORT8850H-2BMN680C

更新时间： 2024-01-23 19:52:46
品牌 Logo 应用领域
莱迪思 - LATTICE 现场可编程门阵列可编程逻辑时钟
页数 文件大小 规格书
105页 1285K
描述
Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver

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ORT8850H-2BMN680C 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：BGA包装说明：LEAD FREE, PLASTIC, FPBGA-680
针数：680Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.63Is Samacsys：N
其他特性：SYSTEM GATES AVAILABLE UPTO 899000最大时钟频率：106.25 MHz
JESD-30 代码：S-PBGA-B680JESD-609代码：e1
长度：35 mm湿度敏感等级：3
等效关口数量：471000端子数量：680
最高工作温度：70 °C最低工作温度：
组织：471000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAY可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：2.51 mm
最大供电电压：1.575 V最小供电电压：1.425 V
标称供电电压：1.5 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM宽度：35 mm
Base Number Matches：1

ORT8850H-2BMN680C 数据手册

 浏览型号ORT8850H-2BMN680C的Datasheet PDF文件第2页浏览型号ORT8850H-2BMN680C的Datasheet PDF文件第3页浏览型号ORT8850H-2BMN680C的Datasheet PDF文件第4页浏览型号ORT8850H-2BMN680C的Datasheet PDF文件第5页浏览型号ORT8850H-2BMN680C的Datasheet PDF文件第6页浏览型号ORT8850H-2BMN680C的Datasheet PDF文件第7页 
ORCA® ORT8850  
Field-Programmable System Chip (FPSC)  
Eight-Channel x 850 Mbits/s Backplane Transceiver  
February 2008  
Data Sheet  
Introduction  
Field Programmable System-on-a-Chip (FPSCs) bring a whole new dimension to programmable logic: Field Pro-  
grammable Gate Array (FPGA) logic and an embedded system solution on a single device. Lattice has developed  
a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high-  
speed serial backplane data transfer. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC)  
architecture, the ORT8850 family is made up of backplane transceivers (SERDES) containing eight channels, each  
operating at up to 850 Mbits/s (6.8 Gbits/s when all eight channels are used). This is combined with a full-duplex  
synchronous interface, with built-in Clock and Data Recovery (CDR) in standard-cell logic, along with over 600K  
usable FPGA system gates (ORT8850H). With the addition of protocol and access logic such as protocol-indepen-  
dent framers, Asynchronous Transfer Mode (ATM) framers, Packet-over-SONET (PoS) interfaces, and framers for  
HDLC for Internet Protocol (IP), designers can build a configurable interface retaining proven backplane  
driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within  
a system that are not SONET/SDH based. For example, designers can build a 6.8 Gbits/s PCI-to-PCI half bridge  
using our PCI soft core.  
The ORT8850 family offers a clockless High-Speed Interface for inter-device communication on a board or across  
a backplane. The built-in clock recovery of the ORT8850 allows for higher system performance, easier-to-design  
clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefit from the  
backplane transceiver as a network termination device. The backplane transceiver offers SONET scram-  
bling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus  
the programmable logic to terminate the network into proprietary systems. For non-SONET applications, all  
SONET functionality is hidden from the user and no prior networking knowledge is required.  
Table 1. ORCA ORT8850 Family – Available FPGA Logic (equivalent to OR4E02 and OR4E06 respectively)  
FPGA  
System  
Gates (K)  
PFU  
FPGA Max  
EBR  
Blocks  
EBR Bits  
(K)  
Device  
PFU Rows Columns Total PFUs User I/Os  
LUTs  
4,992  
ORT8850L  
ORT8850H  
26  
46  
24  
44  
624  
278  
297  
8
74  
201 - 397  
471 - 899  
2,024  
16,192  
16  
148  
Note: The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate  
ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40%  
EBR usage and 2 PLL's. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage  
and 6 PLLs.  
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other  
brand or product names are trademarks or registered trademarks of their respective holders.The specifications and information herein are subject to change without  
notice.  
www.latticesemi.com  
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ort8850_11.1  
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