Data Sheet
February 2002
ORCA® ORT8850 Field-Programmable System Chip (FPSC)
Eight-Channel x 850 Mbits/s Backplane Transceiver
The ORT8850 family offers a clockless high-speed
Introduction
interface for interdevice communication, on a board or
across a backplane. The built-in clock recovery of the
ORT8850 allows for higher system performance, eas-
ier-to-design clock domains in a multiboard system,
and fewer signals on the backplane. Network design-
ers will benefit from the backplane transceiver as a
network termination device. The backplane trans-
ceiver offers SONET scrambling/descrambling of data
and streamlined SONET framing, pointer moving, and
transport overhead handling, plus the programmable
logic to terminate the network into proprietary sys-
tems. For non-SONET application, all SONET func-
tionality is hidden from the user and no prior
networking knowledge is required. The 8850 also
offers 8B/10B coding in addition to SONET scram-
bling.
Field-programmable system chips (FPSCs) bring a
whole new dimension to programmable logic: FPGA
logic and an embedded system solution on a single
device. Lattice has developed a solution for designers
who need the many advantages of FPGA-based
design implementation, coupled with high-speed
serial backplane data transfer. Built on the Series 4
reconfigurable embedded system-on-chips (SoC)
architecture, the ORT8850 family is made up of back-
plane transceivers containing eight channels, each
operating at up to 850 Mbits/s (6.8 Gbits/s when all
eight channels are used) full-duplex synchronous
interface, with built-in clock and data recovery (CDR)
in standard-cell logic, along with up to 600K usable
FPGA system gates. The CDR circuitry is a proven
macrocell available from Lattice’s intellectual property
library, and has already been implemented in numer-
ous applications including ASICs, standard products,
and FPSCs to create interfaces for SONET/SDH STS-
3/STM-1, STS-12/STM-4, STS-48/STM-16, and STS-
192/STM-64 applications.With the addition of protocol
and access logic such as protocol-independent fram-
ers, asynchronous transfer mode (ATM) framers,
packet-over-SONET (POS) interfaces, and framers for
HDLC for Internet protocol (IP), designers can build a
configurable interface retaining proven backplane
driver/receiver technology. Designers can also use the
device to drive high-speed data transfer across buses
within a system that are not SONET/SDH based. For
example, designers can build a 6.8 Gbits/s PCI-to-PCI
half bridge using our PCI soft core.
Also included on the device are three full-duplex, high-
speed parallel interfaces, consisting of 8-bit data, con-
trol (such as start-of-cell), and clock. The interface
delivers double data rate (DDR) data at rates up to
311 MHz (622 Mbits/s per pin), and converts this data
internal to the device into 32-bit wide data running at
half rate on one clock edge. Functions such as center-
ing the transmit clock in the transmit data eye are
done automatically by the interface. Applications
delivered by this interface include a parallel backplane
interface similar to the recently proposed RapidIO™
packet-based interface.
Table 1. ORCA ORT8850 Family—Available FPGA Logic
PFU
Columns
Total
PFUs
FPGA
User I/O
EBR
Blocks
EBR Bits
(K)
Usable
Gates (K)
Device
PFU Rows
LUTs
ORT8850L
ORT8850H
26
46
24
44
624
296
536
4,992
8
74
260—470
530—970
2024
16,192
16
147
Note: The embedded core and interface are not included in the above gate counts.The usable gate counts range from a logic-only gate
count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC
(counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU).
Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used
as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Embedded
block RAM (EBR) is counted as four gates per bit plus each block has an additional 25K gates. 7K gates are used for each PLL and
50K gates for the embedded system bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in
the gate calculations.
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