Datasheet > OR4E02-1BMN680I

OR4E02-1BMN680I

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
莱迪思 - LATTICE		栅
页数	文件大小	规格书
154页	2953K
描述
Field Programmable Gate Array, 624 CLBs, 201000 Gates, 420MHz, CMOS, PBGA680, PLASTIC, FBGA-680

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OR4E02-1BMN680I 数据手册

Data Sheet

May, 2006

ORCA Series 4 FPGAs

■ New double-data rate (DDR) and zero-bus turn-

around (ZBT) memory interfaces support the latest

high-speed memory interfaces.

System Features

■ PCI local bus compliant.

■ New 2x/4x uplink and downlink I/O capabilities inter-

face high-speed external I/Os to reduced speed

internal logic.

■ Improved PowerPC /PowerQUICC MPC860 and

PowerPC II MPC8260 high-speed synchronous

microprocessor interface can be used for conﬁgura-

tion, readback, device control, and device status, as

well as for a general-purpose interface to the FPGA

logic, RAMs, and embedded standard cell blocks.

Glueless interface to synchronous PowerPC proces-

sors with user-conﬁgurable address space provided.

■ Meets universal test and operations PHY interface

for ATM (UTOPIA) Levels 1, 2, and 3. Also meets

proposed speciﬁcations for UTOPIA level 4, POS-

PHY Level 3 (2.5 Gbits/s), and POS-PHY 4 (10

Gbits/s) interface standards for packet-over-SONET

as deﬁned by the Saturn Group.

■ New embedded AMBA™ speciﬁcation 2.0 AHB sys-

tem bus (ARM ™ processor) facilitates communica-

tion among the microprocessor interface,

conﬁguration logic, embedded block RAM, FPGA

logic, and embedded standard cell blocks.

■ ispLEVER development system software. Supported

by industry-standard CAE tools for design entry, syn-

thesis, simulation, and timing analysis.

■ New network PLLs meet ITU-T G.811 speciﬁcations

and provide clock conditioning for DS-1/E-1 and

STS-3/STM-1 applications.

■ Variable size bused readback of conﬁguration data

capability with the built-in microprocessor interface

and system bus.

■ Internal, 3-state, bidirectional buses with simple con-

trol provided by the SLIC.

■ New clock routing structures for global and local

clocking signiﬁcantly increases speed and reduces

skew (<200 ps for OR4E04).

■ New local clock routing structures allow creation of

localized clock trees.

■ Two new edge clock routing structures allow up to six

high-speed clocks on each edge of the device for

improved setup/hold and clock to out performance.

Lattice Semiconductor

1...3 4 567 8 9...154

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