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OPTIMIZING

更新时间： 2024-11-04 23:24:43

品牌	Logo	应用领域
其他 - ETC		驱动器
页数	文件大小	规格书
6页	126K
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Optimizing Output Configuration of Semtech Bipolar Pin Drivers (126k)

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OPTIMIZING 数据手册

PE-A2

Optimizing the Output Configuration of

Semtech Bipolar Pin Drivers

TEST AND MEASUREMENT PRODUCTS

Background: Connecting a Pin Driver to a Test Device

Ideally, the Driver output from a Driver/Comparator/Load

(DCL) IC would be connected to the Device Under Test

(DUT) pin with a perfect transmission line. The most

common connection scheme is for the DCL to be

impedance-matched to the transmission line while the

DUT end of the line is unterminated. In this case, the

driver waveform would be exactly reproduced at the DUT,

and DUT waveforms would be perfectly reproduced at the

Comparator. This perfect transmission line includes perfect

impedance matching at the DCL end as well as no parasitic

resistance, capacitance or inductance anywhere along the

line.

If the real impedance is correctly matched, but there is a

capacitive or inductive mismatch (imaginary portion of the

source impedance), then there will be a glitch in the

waveform when driving an unterminated transmission line

as shown in Figure 2. This effect is greatest at the fastest

rise/fall times, so checking and optimizing this behavior

should be done at the fastest slew rates of interest.

Note that when the L-C balance is correct, the amount of

slowing of the rise/fall times caused by the impedance

mismatch is minimized. This can be seen by expanding

Figure 2 around the pulse rising edge as done in Figure 3.

The amount of improvement will be maximized for the

fastest rise/fall times.

In practice, there are usually a number of things which

degrade the AC performance. For instance, if the source

impedance of the DCL is not perfectly matched to the

transmission line impedance, there will be amplitude errors

in the waveform. If the low frequency (real) portion of the

source impedance is incorrect, then there will be a step

in the wa ve form whe n driving a n unte rmina te d

transmission line, as shown in Figure 1.

DC Impedance Matching

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-0.5

R-out<50 ohms

R-out=50 ohms

R-out>50 ohms

0.0

5.0

10.0

15.0

20.0

Time(ns)

Figure 1. Typical Waveforms When Driving a 3.3V Signal into a

50Ω Transmission Line with Varying DC Source Impedance

www .semtech.com

Revision 1 / December 18, 2002

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