0
OPB 16450 UART
0
0
DS433 August 18, 2004
Product Specification
Introduction
This document provides the specification for the OPB Uni-
versal Asynchronous Receiver/Transmitter (UART) Intellec-
tual Property (IP).
LogiCORE™ Facts
Core Specifics
Virtex-II Pro , Virtex ,
™
™
Supported Device
Family
™
™
™
Virtex-II , Virtex-4 , QPro -R
Virtex-II, QPro Virtex-II, Virtex-E,
The UART described in this document has been designed
incorporating the features described in National Semicon-
ductor PC16550D UART with FIFOs data sheet (June,
1995), (http://www.national.com/pf/PC/PC16550D.html).
™
™
Spartan-II , Spartan-IIE ,
™
Spartan-3
Version of Core
opb_uart16450
v1.00c
The National Semiconductor PC16550D data sheet is refer-
enced throughout this document and should be used as the
authoritative specification. Differences between the
National Semiconductor implementation and the OPB
UART Point Design implementation are highlighted and
explained in Specification Exceptions
Resources Used
Min
Max
341
357
347
0
Slices
341
LUTs
357
Features
FFs
347
•
Hardware and software register compatible with all
standard 16450 UARTs
Block RAMs
0
•
Implements all standard serial interface protocols
Provided with Core
-
-
-
-
5, 6, 7, or 8 bits per character
Documentation
Design File Formats
Constraints File
Verification
Product Specification.
Odd, Even, or no parity detection and generation
1, 1.5, or 2 stop bit detection and generation
VHDL
N/A
Internal baud rate generator and separate receiver
clock input
N/A
-
-
-
Modem control functions
Instantiation
Template
N/A
False start bit detection and recovery
Prioritized transmit, receive, line status, and
modem control interrupts
Reference Designs
None
-
-
Line break detection and generation
Design Tool Requirements
Internal loop back diagnostic functionality
XilinxImplementation
Tools
5.1i or later
•
Registers
-
-
-
-
-
-
Receiver Buffer Register (Read Only)
Verification
Simulation
Synthesis
N/A
Transmitter Holding Register (Write Only)
Interrupt Enable Register
ModelSim SE/EE 5.6e or later
XST
Interrupt Identification Register (Read Only)
Line Control and Line Status Registers
Modem Control and Modem Status Registers
Support
Support provided by Xilinx, Inc.
Divisor Latch (least and more significant byte)
•
Scratch Register
-
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS433 August 18, 2004
www.xilinx.com
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Product Specification
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