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OCX160 PDF预览

OCX160

更新时间: 2024-02-20 17:07:47
品牌 Logo 应用领域
其他 - ETC 开关
页数 文件大小 规格书
44页 666K
描述
OCX160 Crosspoint Switch

OCX160 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:LBGA,针数:420
Reach Compliance Code:unknown风险等级:5.67
边界扫描:YESJESD-30 代码:S-PBGA-B420
长度:35 mm低功率模式:YES
端子数量:420最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE认证状态:Not Qualified
座面最大高度:1.7 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:35 mmuPs/uCs/外围集成电路类型:DSP PERIPHERAL, CROSSBAR SWITCH
Base Number Matches:1

OCX160 数据手册

 浏览型号OCX160的Datasheet PDF文件第2页浏览型号OCX160的Datasheet PDF文件第3页浏览型号OCX160的Datasheet PDF文件第4页浏览型号OCX160的Datasheet PDF文件第5页浏览型号OCX160的Datasheet PDF文件第6页浏览型号OCX160的Datasheet PDF文件第7页 
OCX160 Crosspoint Switch  
Preliminary Data Sheet  
Features  
667 Mb/s port data bandwidth, >50Gb/s aggregate bandwidth Full Broadcast and multicast capability  
One-to-One and One-to-Many connections  
Special broadcast mode routes one input to  
all outputs at maximum data rate  
Low power CMOS, 2.5V and 3.3V power supply  
SRAM-based, in-system programmable  
160 configurable I/O ports  
Registered and flow-through data modes  
333 MHz synchronous mode  
667 Mb/s asynchronous mode  
Low jitter and signal skew  
80 dedicated differential input ports  
80 dedicated differential output ports  
Supports LVDS and LVPECL I/O  
LVTTL control interface  
Low duty cycle distortion  
Output Enable control for all outputs  
RapidConfigureparallel interface for  
configuration and readback  
Non-blocking switch matrix  
Patented ActiveArraymatrix for superior performance  
Double-buffered configuration RAM cells for simultaneous  
global updates  
JTAG serial interface for configuration and  
Boundary Scan testing  
ImpliedDisconnectfunction for single cycle disconnect/ 420 BGA package with 1.27mm ball spacing  
connect  
Description  
The OCX™ family of SRAM-based devices are non-blocking n X n digital crosspoint switches capable of data  
rates of 667 Megabits per second per port. The I/O ports are fixed as either input or output ports. The input ports  
support flow-through mode only. The output ports are individually programmable to operate in either flow-  
through (asynchronous) or registered (synchronous) mode. Each output register may be clocked by a global  
clock or a next neighbor clock source.  
The patented ActiveArray provides greater density, superior performance, and greater flexibility compared to a  
traditional n:1 multiplexer architecture. The OCX devices support various operating modes covering one input to  
one output at a time as well as one input to many outputs, plus a special broadcast mode to program one input to  
all outputs while maintaining maximum data rates. In all modes data integrity and connections are maintained on  
all unchanged data paths.  
The RapidConfigure parallel interface allows fast configuration of both the Output Buffers and the switch  
matrix. Readback is supported for device test and verification purposes. The OCX160 also supports the industry  
standard JTAG (IEEE 1149.1) interface for boundary scan testing. The JTAG interface can also be used to  
download configuration data to the device and readback data. A functional block diagram of the OCX160 is  
shown in Figure 1.  
Applications  
SONET/SDH and DWDM  
Digital Cross-Connects  
System Backplanes and Interconnects  
High Speed Test Equipment  
ATM Switch Cores  
Video Switching  
160  
160  
IN[79:0]  
OUT[79:0]  
80 x 80  
Crosspoint  
Switch Matrix  
Input  
Buffers  
Output  
Buffers  
2
CLK  
OE#  
7
RCA[6:0]  
RCB[6:0]  
RCI[3:0]  
TCK  
TMS  
TDI  
7
4
JTAG  
Signals  
RapidConfigure  
Signals  
Configuration and  
Programming Logic  
RCO[4:0]  
RC_CLK#  
RC_EN#  
5
TRST#  
TDO  
HW_RST#  
UPDATE#  
Figure 1 OCX160 Functional Block Diagram  
I-Cube, Inc.  
[Rev. 1.6] 2/20/01  
1

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