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NUS5530MNR2G

更新时间： 2024-11-25 03:45:47
品牌 Logo 应用领域
安森美 - ONSEMI 晶体开关晶体管功率场效应晶体管脉冲光电二极管
页数 文件大小 规格书
9页 163K
描述
Integrated Power MOSFET with PNP Low VCE(sat) Switching Transistor

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中文翻译

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NUS5530MNR2G 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：DFN包装说明：SMALL OUTLINE, R-PDSO-N8
针数：8Reach Compliance Code：compliant
ECCN代码：EAR99Factory Lead Time：1 week
风险等级：5.31最大集电极电流 (IC)：2 A
配置：SINGLE WITH BUILT-IN BIPOLAR TRANSISTOR AND DIODE最小直流电流增益 (hFE)：100
最小漏源击穿电压：20 V最大漏极电流 (ID)：3.9 A
最大漏源导通电阻：0.083 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
最大降落时间（tf）：70 nsJESD-30 代码：R-PDSO-N8
JESD-609代码：e3湿度敏感等级：1
元件数量：1端子数量：8
工作模式：ENHANCEMENT MODE最高工作温度：150 °C
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
极性/信道类型：P-CHANNEL最大功率耗散 (Abs)：0.635 W
最大脉冲漏极电流 (IDM)：20 A认证状态：Not Qualified
最大上升时间（tr）：55 ns子类别：Other Transistors
表面贴装：YES端子面层：Tin (Sn)
端子形式：NO LEAD端子位置：DUAL
处于峰值回流温度下的最长时间：40晶体管应用：SWITCHING
晶体管元件材料：SILICONVCEsat-Max：0.3 V
Base Number Matches：1

NUS5530MNR2G 数据手册

 浏览型号NUS5530MNR2G的Datasheet PDF文件第2页浏览型号NUS5530MNR2G的Datasheet PDF文件第3页浏览型号NUS5530MNR2G的Datasheet PDF文件第4页浏览型号NUS5530MNR2G的Datasheet PDF文件第5页浏览型号NUS5530MNR2G的Datasheet PDF文件第6页浏览型号NUS5530MNR2G的Datasheet PDF文件第7页 
NUS5530MN  
Integrated Power MOSFET  
with PNP Low VCE(sat)  
Switching Transistor  
This integrated device represents a new level of safety and  
board−space reduction by combining the 20 V P−Channel FET with a  
http://onsemi.com  
PNP Silicon Low V  
switching transistor. This newly integrated  
CE(sat)  
product provides higher efficiency and accuracy for battery powered  
portable electronics.  
1
2
3
4
8
7
6
5
Features  
• Low R  
(MOSFET) and Low V  
(Transistor)  
DS(on)  
CE(sat)  
• Higher Efficiency Extending Battery Life  
• Logic Level Gate Drive (MOSFET)  
• Performance DFN Package  
• This is a Pb−Free Device  
Applications  
(Top View)  
• Power Management in Portable and Battery−Powered Products; i.e.,  
Cellular and Cordless Telephones and PCMCIA Cards  
MARKING DIAGRAM  
8
MAXIMUM RATINGS FOR P−CHANNEL FET  
A
1
5530  
(T = 25°C unless otherwise noted)  
1
AYWW G  
Steady  
State  
DFN8  
CASE 506AL  
G
Rating  
Drain−Source Voltage  
Gate−Source Voltage  
Continuous Drain Current  
Symbol  
5 sec  
Unit  
V
V
DS  
V
GS  
−20  
A
Y
WW  
G
= Assembly Location  
"12  
V
= Year  
= Work Week  
= Pb−Free Package  
I
A
D
(T = 150°C) (Note 1)  
J
T = 25°C  
−5.3  
−3.8  
−3.9  
−2.8  
A
T = 85°C  
(Note: Microdot may be in either location)  
A
Pulsed Drain Current  
I
"20  
A
A
DM  
PIN ASSIGNMENT  
Continuous Source Current  
(Note 1)  
I
−5.3  
−3.9  
S
Emitter  
Base  
8
7
6
5
1
2
3
4
N/C  
Collector  
Maximum Power Dissipation  
(Note 1)  
P
W
D
Collector  
Source  
Drain  
T = 25°C  
2.5  
1.3  
1.3  
0.7  
A
T = 85°C  
N/C  
A
Drain  
Operating Junction and Storage  
Temperature Range  
T , T  
J
−55 to +150  
°C  
stg  
Gate  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
(Bottom View)  
ORDERING INFORMATION  
†
Device  
NUS5530MNR2G  
Package  
Shipping  
1. Surface Mounted on FR4 Board using 1 in sq pad size  
(Cu area = 1.27 in sq [1 oz] including traces).  
DFN8  
3000/Tape & Reel  
(Pb−Free)  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specifications  
Brochure, BRD8011/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
May, 2006 − Rev. 0  
NUS5530MN/D  
1234567...9

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