Nanya Technology Corp.
LPDDR 512Mb SDRAM
NT6DM32M16BD / NT6DM16M32BC
NT6DM32M16BD / NT6DM16M32BC
Commercial and Industrial Mobile DDR 512Mb SDRAM
Features
Data Integrity
JEDEC LPDDR Compliant
- Low Power Consumption
- DRAM built-in Temperature Sensor for
Temperature Compensated Self Refresh (TCSR)
- 2n Prefetch Architecture
- Auto Refresh and Self Refresh Modes
Power Saving Mode
- Differential clock inputs (CK and )
- Double-data rate on DQs, DQS and DM
- Commands entered on each positive CK edge
- Deep Power Down Mode (DPD)
- Partial Array Self Refresh (PASR)
- Clock Stop capability during idle period
LVCMOS Interface and Power Supply
- VDD/VDDQ=1.70 to 1.95V
- DQS edge-aligned with data for READs;
center-aligned with data for WRITEs
- Status Register Read (SRR)
Signal Integrity
- Configurable DS for system compatibility
Options
Speed Grade (CL-TRCD-TRP) 1
Temperature Range (Tc)
- Commercial Grade = -25℃~85℃
- Industrial Grade = -40℃~85℃
- 333 Mbps / 3-3-3
- 400 Mbps / 3-3-3
Programmable Functions
Burst Type (Sequential, Interleaved)
Driver Strength (full, 1/2, 3/4, 1/4)
CAS Latency (2, 3)
Burst Length (2, 4, 8, 16)
Packages / Density Information
Density and Addressing
512Mb
Lead-free RoHS compliance and Halogen-free
Item
512Mb
Length x Width
(mm)
Ball pitch
(mm)
(Org / Package)
Addressing
Organization
Number of banks
Bank Address
Auto precharge
Row Address
Column Address
tRFC(ns) 2
Standard
Reduced Page Size
32M x 16 16M x 32
16M x 32
4
4
4
60-ball
32Mx16
8.00 x 9.00
0.80
0.80
BA0,BA1 BA0,BA1
BA0,BA1
A10/AP
A0-A13
A0-A7
110
VFBGA
A10/AP
A0-A12
A0-A9
110
A10/AP
A0-A12
A0-A8
110
90-ball
16Mx32
8.00 x 13.00
VFBGA
tREFI (µs) 3
7.8
7.8
7.8
Notes:
1. The timing specification of high speed bin is backward compatible with low speed bin.
2. Violating tRFC specification will induce malfunction.
3. tREFI values for all bank refresh is within temperature specification(<= 85℃).
Version 1.4
01/2016
1
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NTC has the rights to change any specification or product without notification.