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NT6CL128T64DR-H1 PDF预览

NT6CL128T64DR-H1

更新时间: 2024-11-09 02:45:23
品牌 Logo 应用领域
南亚科技 - NANYA 动态存储器双倍数据速率光电二极管
页数 文件大小 规格书
157页 5702K
描述
Commercial Mobile LPDDR3 4Gb / 8Gb(DDP) SDRAM

NT6CL128T64DR-H1 数据手册

 浏览型号NT6CL128T64DR-H1的Datasheet PDF文件第2页浏览型号NT6CL128T64DR-H1的Datasheet PDF文件第3页浏览型号NT6CL128T64DR-H1的Datasheet PDF文件第4页浏览型号NT6CL128T64DR-H1的Datasheet PDF文件第5页浏览型号NT6CL128T64DR-H1的Datasheet PDF文件第6页浏览型号NT6CL128T64DR-H1的Datasheet PDF文件第7页 
NTC Proprietary  
Level: Property  
Preliminary  
LPDDR3 4Gb/8Gb(DDP) SDRAM  
4Gb:NT6CL128M32DM(Q), NT6CL256M16DM  
8Gb: NT6CL128T64DR(4)  
Commercial Mobile LPDDR3 4Gb / 8Gb(DDP) SDRAM  
Features  
Data Integrity  
Basis LPDDR3 Compliant  
- Low Power Consumption  
- DRAM built-in Temperature Sensor for  
Temperature Compensated Self Refresh (TCSR)  
- 8n Prefetch Architecture and BL8 only  
- Auto Refresh and Self Refresh Modes  
Power Saving Modes  
Signal Integrity  
- Configurable DS for system compatibility  
- Configurable On-Die Termination1  
- Deep Power Down Mode (DPD)  
- Partial Array Self Refresh (PASR)  
- Clock Stop capability during idle period  
HSUL12 interface and Power Supply  
- VDD1= 1.70 to 1.95V  
- ZQ Calibration for DS/ODT impedance accuracy via  
external ZQ pad (240Ω± 1%)  
Training for SignalsSynchronization  
- DQ Calibration offering specific DQ output patterns  
- CA Training  
- Write Leveling via MR settings 2  
- VDD2/VDDQ/VDDCA = 1.14 to 1.3V  
Programmable functions  
RL/WL Select (Set A / Set B)  
nWRE ( nWR9 / nWR>9)  
PASR (bank/segment)  
RON (Typical:34.3/40/48/60/80)  
RON (PD34.3_PU40 / PD40_PU48 / PD34.3_PU48)  
RTT (120/240)  
Options  
Temperature Range (Tc)  
Speed Grade (DataRate/Read Latency)  
- Commercial Grade : - 30to +85, extending 1054  
- 1866 Mbps / RL=14  
Package Information  
Density, Signals and Addressing  
Lead-free RoHS compliance and Halogen-free  
4Gb (SDP)  
X16 X32  
8Gb (DDP)  
X64(2ch)  
Items  
(FBGA Package)  
Width x Length x Height  
(mm)  
Ball pitch  
(mm)  
Items  
  
CK//CKE  
DQ  
  
_a/b  
CK /  / CKE_a/b  
[31:0] _a/b  
168b PoP  
178b  
CK /  / CKE  
12.00 x 12.00 x 0.83  
10.50 x 11.50 x 0.83  
12.00 x 12.00 x 0.83  
14.00 x 14.00 x 0.83  
0.50  
[15:0]  
[1:0] / [1:0]  
CA[9:0]  
[31:0]  
DQS/DM  
CA  
[3:0] / [3:0]  
[3:0] _a/b / [3:0] _a/b  
CA[9:0] _a/b  
0.65/0.80  
Mixed  
Bank Addr.  
Row Addr.3  
Column Addr.3  
Tc85  
BA[2:0]  
R[13:0]  
C[9:0]  
216b PoP  
256b PoP  
0.40  
0.40  
C[10:0]  
C[9:0]  
3.9μs  
tREFI  
85<Tc95℃  
95<Tc105℃  
1.95μs  
0.975μs  
NOTE 1 Depending on ballout, ODT pin may be NOT supported so ODT die pad is connected to Vss inside the package.  
NOTE 2 Write Leveling DQ feedback on all DQs  
NOTE 3 Row and Column Addresses values on the CA bus that are not used are “don’t care.”  
NOTE 4 AC/DC will be derated when above 85 oC  
1
Version 1.2  
Nanya Technology Corp.  
12/2018  
All Rights Reserved ©  
NTC has the rights to change any specifications or product herein without notification.  

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