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NS41256S20E/883 PDF预览

NS41256S20E/883

更新时间: 2024-02-02 13:15:36
品牌 Logo 应用领域
德州仪器 - TI 静态存储器内存集成电路
页数 文件大小 规格书
18页 40K
描述
32KX8 STANDARD SRAM, 20ns, CQCC32, 0.450 X 0.550 INCH, CERAMIC, LCC-32

NS41256S20E/883 技术参数

生命周期:Obsolete包装说明:QCCN, LCC32,.45X.55
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.6
Is Samacsys:N最长访问时间:20 ns
I/O 类型:COMMONJESD-30 代码:R-CQCC-N32
内存密度:262144 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:32字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:32KX8输出特性:3-STATE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC32,.45X.55封装形状:RECTANGULAR
封装形式:CHIP CARRIER并行/串行:PARALLEL
电源:5 V认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B最大待机电流:0.02 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.17 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
Base Number Matches:1

NS41256S20E/883 数据手册

 浏览型号NS41256S20E/883的Datasheet PDF文件第3页浏览型号NS41256S20E/883的Datasheet PDF文件第4页浏览型号NS41256S20E/883的Datasheet PDF文件第5页浏览型号NS41256S20E/883的Datasheet PDF文件第7页浏览型号NS41256S20E/883的Datasheet PDF文件第8页浏览型号NS41256S20E/883的Datasheet PDF文件第9页 
MICROCIRCUIT DATA SHEET  
MNNS41256S20-X REV 0A0  
Electrical Characteristics  
AC PARAMETERS: ELECTRICAL CHARACTERISTICS(Continued)  
(The following conditions apply to all the following parameters, unless otherwise specified.)  
AC: Vcc=5V +10%, TA=-55 C to +125 C, Input pulse levels=Gnd to 3.0V, Input rise and fall times=5nS, Input  
timing reference levels=1.5V, Output reference levels=1.5V, Output load for 12-35nS speed grades=See  
fig. 1 & 2.  
PIN-  
NAME  
SUB-  
SYMBOL  
tLZWE  
tHZWE  
PARAMETER  
CONDITIONS  
NOTES  
MIN  
MAX UNIT  
GROUPS  
Write Disable to  
Output in Low Z  
4, 5  
0
nS  
9, 10,  
11  
Write Enable to  
Output in High Z  
4, 5  
3
nS  
9, 10,  
11  
AC PARAMETERS: Capacitance  
(The following conditions apply to all the following parameters, unless otherwise specified.)  
AC: TA=+25 C, f=1.0Mhz  
Cin  
Input Capacitance  
7
8
pF  
pF  
9, 10,  
11  
Cout  
Output  
Capacitance  
7
8
9, 10,  
11  
Note 1: The device is continuously selected. All the Chip Enables are held in their active  
state.  
Note 2: The address is valid prior to or coincident with the latest occuring Chip Enable.  
Note 3: At any given temperature and voltage condition, tHZCE is less than tLZCE.  
Note 4: This parameter is sampled.  
Note 5: The parameter is tested with CL=5pF as shown in Figure 2. Transition is measured  
+200mV from steady state voltage.  
Note 6: Vil(Min)=-3.0V for pulse width less than 20nS.  
Note 7: This parameter is determined by device characterization but is not production tested.  
6

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