Datasheet > NS41024S55E-SMD

NS41024S55E-SMD

更新时间： 2024-01-24 14:25:47

品牌	Logo	应用领域
美国国家半导体 - NSC		静态存储器内存集成电路
页数	文件大小	规格书
16页	42K
描述
IC,SRAM,128KX8,CMOS,LLCC,32PIN,CERAMIC

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NS41024S55E-SMD 技术参数

生命周期：	Obsolete	包装说明：	QCCN, LCC32,.45X.55
Reach Compliance Code：	unknown	风险等级：	5.84
最长访问时间：	55 ns	I/O 类型：	COMMON
JESD-30 代码：	R-XQCC-N32	内存密度：	1048576 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	8
端子数量：	32	字数：	131072 words
字数代码：	128000	工作模式：	ASYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	128KX8	输出特性：	3-STATE
封装主体材料：	CERAMIC	封装代码：	QCCN
封装等效代码：	LCC32,.45X.55	封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER	并行/串行：	PARALLEL
电源：	5 V	认证状态：	Not Qualified
筛选级别：	38535Q/M;38534H;883B	最大待机电流：	0.01 A
最小待机电流：	4.5 V	子类别：	SRAMs
最大压摆率：	0.125 mA	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	QUAD
Base Number Matches：	1

NS41024S55E-SMD 数据手册

MICROCIRCUIT DATA SHEET

MDNS41024S55-X REV 0B0

Electrical Characteristics

AC PARAMETERS: ELECTRICAL CHARACTERISTICS(Continued)

(The following conditions apply to all the following parameters, unless otherwise specified.)

AC: -55 C < Tc < +125 C, Vss = 0V, 4.5V < Vcc < 5.5V

PIN-

NAME

SUB-

SYMBOL

tWLQZ

PARAMETER

CONDITIONS

NOTES

MIN

MAX UNIT

GROUPS

Write Enable to

Output Disable

9, 10,

5, 8

tWHQX

Output Active

after end of

Write

9, 10,

5, 8

Data Retention Electrical Characteristics: AC

(The following conditions apply to all the following parameters, unless otherwise specified.)

AC: -55 C < Tc < +125 C, Vss = 0V, 4.5V < Vcc < 5.5V

tCDR

Retention Time

9, 10,

4, 8

Operation

Recovery Time

9, 10,

4, 8

Note 1: This parameter is tested initially and after any design or process change which could

affect this parameter, and therefore shall be guaranteed to the limits specified in

table 1.

Note 2: Functional tests shall include the test table and other test patterns used for fault

detection as approved by the qualifying activity. Outputs are measured at Vol < 1.5V,

Voh > 1.5V.

Note 3: For timing waveforms see Figure 4 and for output load circuits, see figure 5.

Note 4: AC measurements assume transition time < 5nS, input levels are from ground to 3.0V,

and output load Cl > 30pF except as noted on figure 5. Timing reference Levels are

1.5V.

Note 5: Transition is measured +500 mV from steady state voltage.

Note 6: Subgroup 4 (Cin and Cout measurements) shall be measured only for initial

qualification and after any process or design changes which may affect input or

output capacitance. Capacitance shall be measured between the designated terminal and

Gnd at a frequency of 1 MHz. Sample size is 15 devices with no failures, and all

input and output terminals tested.

Note 7: For device class M subgroups 7 and 8 tests shall be sufficient to verify the truth

table. For device classed B and S subgroups 7 and 8 tests shall be sufficient to

verify the truth table as approved by the qualifying activity. For device classes Q

and V subgroups 7 and 8 shall include verifying the functionality of the device;

these tests shall have been fault graded in accordance with MIL-STD-883, test method

5012.

Note 8: See figure 4, as applicable.

1...3 4 567 8 9...16

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NS41256L15J/883	TI	32KX8 STANDARD SRAM, 15ns, CDIP28, 0.300 INCH, CERDIP-28	获取价格
NS41256L20J/883	TI	32KX8 STANDARD SRAM, 20ns, CDIP28, 0.300 INCH, CERDIP-28	获取价格
NS41256L25J/883	TI	32KX8 STANDARD SRAM, 25ns, CDIP28, 0.300 INCH, CERDIP-28	获取价格
NS41256L35E/883	TI	32KX8 STANDARD SRAM, 35ns, CQCC32, 0.450 X 0.550 INCH, CERAMIC, LCC-32	获取价格

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