2.0 Architectural Description (Continued)
2.1.2.1 FSR Mode Control Fields
010 Overflow. A result (either floating-point or integer) of a
floating-point instruction is too great in magnitude to
be held in the format of the destination operand. Note
that rounding, as well as calculations, can cause this
condition.
The FSR mode control fields select FPU operation modes.
The meanings of the FSR mode control bits are given be-
low.
Rounding Mode (RM): Bits 7 and 8. This field selects the
rounding method. Floating-point results are rounded when-
ever they cannot be exactly represented. The rounding
modes are:
011 Divide by zero. An attempt has been made to divide a
non-zero floating-point number by zero. Dividing zero
by zero is considered an Invalid Operation instead
(below).
00 Round to nearest value. The value which is nearest to
the exact result is returned. If the result is exactly half-
way between the two nearest values the even value
100 Illegal Instruction. Any instruction forms not included
in the NS32381 Instruction Set are detected by the
FPU as being illegal.
e
(LSB 0) is returned.
101 Invalid Operation. One of the floating-point operands
of a floating-point instruction is a Reserved operand,
or an attempt has been made to divide zero by zero
using the DIVf instruction.
01 Round toward zero. The nearest value which is closer
to zero or equal to the exact result is returned.
10 Round toward positive infinity. The nearest value which
is greater than or equal to the exact result is returned.
110 Inexact Result. The result (either floating-point or inte-
ger) of a floating-point instruction cannot be repre-
sented exactly in the format of the destination oper-
and, and a rounding step must alter it to fit. This condi-
tion is always reported in the TT field and IF bit unless
any other exceptional condition has occurred in the
same instruction. In this case, the TT field always con-
tains the code for the other exception and the IF bit is
not altered. A trap is caused by this condition only if
the IEN bit is set; otherwise the result is rounded and
delivered, and no trap occurs.
11 Round toward negative infinity. The nearest value
which is less than or equal to the exact result is re-
turned.
Underflow Trap Enable (UEN): Bit 3. If this bit is set, the
FPU requests a trap whenever a result is too small in abso-
lute value to be represented as a normalized number. If it is
not set, any underflow condition returns a result of exactly
zero.
Inexact Result Trap Enable (IEN): Bit 5. If this bit is set,
the FPU requests a trap whenever the result of an operation
cannot be represented exactly in the operand format of the
destination. If it is not set, the result is rounded according to
the selected rounding mode.
111 (Reserved for future use.)
Underflow Flag (UF): Bit 4. This bit is set by the FPU when-
ever a result is too small in absolute value to be represented
as a normalized number. Its function is not affected by the
state of the UEN bit. The UF bit is cleared only by writing a
zero into it with the Load FSR instruction or by a hardware
reset.
2.1.2.2 FSR Status Fields
The FSR Status Fields record exceptional conditions en-
countered during floating-point data processing. The mean-
ings of the FSR status bits are given below:
Inexact Result Flag (IF): Bit 6. This bit is set by the FPU
whenever the result of an operation must be rounded to fit
within the destination format. The IF bit is set only if no other
error has occurred. It is cleared only by writing a zero into it
with the Load FSR instruction or by a hardware reset.
Trap Type (TT): bits 0-2. This 3-bit field records any excep-
tional condition detected by a floating-point instruction. The
TT field is loaded with zero whenever any floating-point in-
struction except LFSR or SFSR completes without encoun-
tering an exceptional condition. It is also set to zero by a
hardware reset or by writing zero into it with the Load FSR
(LFSR) instruction. Underflow and Inexact Result are always
reported in the TT field, regardless of the settings of the
UEN and IEN bits.
Register Modify Bit (RMB): Bit 16. This bit is set by the
FPU whenever writing to a floating point data register. The
RMB bit is cleared only by writing a zero with the LFSR
instruction or by a hardware reset. This bit can be used in
context switching to determine whether the FPU registers
should be saved.
000 No exceptional condition occurred.
001 Underflow. A non-zero floating-point result is too small
in magnitude to be represented as a normalized float-
ing-point number in the format of the destination oper-
and. This condition is always reported in the TT field
and UF bit, but causes a trap only if the UEN bit is set.
If the UEN bit is not set, a result of Positive Zero is
produced, and no trap occurs.
2.1.2.3 FSR Software Field (SWF)
Bits 9-15 of the FSR hold and display any information writ-
ten to them (using the LFSR and SFSR instructions), but are
not otherwise used by FPU hardware. They are reserved for
use with NSC floating-point extension software.
7
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