Datasheet > NP15P06SLG_15

NP15P06SLG_15

更新时间： 2022-02-26 12:23:17

品牌	Logo	应用领域
瑞萨 - RENESAS		开关
页数	文件大小	规格书
9页	306K
描述
SWITCHING P-CHANNEL POWER MOS FET

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NP15P06SLG_15 数据手册

NP15P06SLG

ELECTRICAL CHARACTERISTICS (TA = 25°C)

CHARACTERISTICS

Zero Gate Voltage Drain Current

Gate Leakage Current

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

−10

UNIT

μA

IDSS

VDS = −60 V, VGS = 0 V

IGSS

VGS = m20 V, VDS = 0 V

VDS = VGS, ID = −250 μA

VDS = −10 V, ID = −7.5 A

VGS = −10 V, ID = −7.5 A

VGS = −4.5 V, ID = −7.5 A

VDS = −10 V,

m10

Gate to Source Threshold Voltage

Forward Transfer Admittance ^Note

Drain to Source On-state Resistance ^Note

VGS(th)

| y^fs|

R^DS(on)1

RDS(on)2

Ciss

−1.0

−1.6

−2.5

<R>

mΩ

Input Capacitance

1100

150

100

Output Capacitance

Reverse Transfer Capacitance

Turn-on Delay Time

Rise Time

Coss

Crss

VGS = 0 V,

f = 1 MHz

td(on)

VDD = −30 V, ID = −7.5 A,

VGS = −10 V,

Turn-off Delay Time

Fall Time

td(off)

RG = 0 Ω

100

Total Gate Charge

VDD = −48 V,

Gate to Source Charge

Gate to Drain Charge

Body Diode Forward Voltage ^Note

Reverse Recovery Time

Reverse Recovery Charge

QGS

QGD

V^F(S-D)

trr

VGS = −10 V,

<R>

ID = −15 A

IF = −15 A, VGS = 0 V

IF = −15 A, VGS = 0 V,

di/dt = −100 A/μs

0.96

1.5

Qrr

Note Pulsed test PW ≤ 350 μs, Duty Cycle ≤ 2%

TEST CIRCUIT 2 SWITCHING TIME

TEST CIRCUIT 1 AVALANCHE CAPABILITY

D.U.T.

= 25 Ω

GS(−)

90%

10%

50 Ω

PG.

GS = −20 → 0 V

Wave Form

PG.

DS(−)

90%

−

BV^DSS

GS(−)

10% 10%

Wave Form

d(on)

d(off)

VDD

off

τ = 1

Starting Tch

Duty Cycle ≤ 1%

TEST CIRCUIT 3 GATE CHARGE

D.U.T.

= −2 mA

PG.

50 Ω

Data Sheet D19078EJ2V0DS

1 2 345 6 7...9

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