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NM24W02LN PDF预览

NM24W02LN

更新时间: 2024-11-11 23:53:59
品牌 Logo 应用领域
其他 - ETC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
14页 151K
描述
I2C Serial EEPROM

NM24W02LN 数据手册

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PRELIMINARY  
March 1999  
NM24Wxx  
2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface  
Serial EEPROM with Full Array Write Protect  
General Description  
Features  
The NM24Wxx devices are 2048/4096/8192/16,384 bits, respec-  
tively, of CMOS non-volatile electrically erasable memory. These  
devices conform to all specifications in the IIC 2-wire protocol and  
are designed to minimize device pin count, and simplify PC board  
layout requirements.  
Hardware Write Protect for entire memory  
Low Power CMOS  
200µA active current typical  
10µA standby current typical  
1µA standby typical (L)  
0.1µA standby typical (LZ)  
The entire ememory can be disabled (Write Protected) by con-  
nectingtheWPpintoVCC.Thememorythenbecomesunalterable  
IIC Compatible interface  
unless WP is switched to VSS  
.
— Provides bidirectional data transfer protocol  
Sixteen byte page write mode  
— Minimizes total write time per byte  
This communications protocol uses CLOCK (SCL) and DATA  
I/O (SDA) lines to synchronously clock data between the master  
(forexampleamicroprocessor)andtheslaveEEPROMdevice(s).  
The Standard IIC protocol allows for a maximum of 16K of  
EEPROM memory which is supported by Fairchild's family in 2K,  
4K, 8K, and 16K devices, allowing the user to configure the  
memory as the application requires with any combination of  
EEPROMs.  
Self timed write cycle  
— Typical write cycle time of 6ms  
Endurance: 1,000,000 data changes  
Data retention greater than 40 years  
Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP  
Available in three temperature ranges  
- Commercial: 0° to +70°C  
Fairchild EEPROMs are designed and tested for applications  
requiringhighendurance, highreliabilityandlowpowerconsump-  
tion.  
- Extended (E): -40° to +85C  
- Automotive (V): -40° to +125°C  
Block Diagram  
V
CC  
V
SS  
WP  
H.V. GENERATION  
TIMING &CONTROL  
START CYCLE  
START  
STOP  
SDA  
LOGIC  
CONTROL  
LOGIC  
SLAVE ADDRESS  
REGISTER &  
COMPARATOR  
16/  
32/  
64/  
2
E
PROM  
ARRAY  
XDEC  
SCL  
128/  
LOAD  
INC  
A2  
A1  
A0  
WORD  
ADDRESS  
COUNTER  
0/1/2/3  
4
16  
4
R/W  
YDEC  
Device Address Bits  
8
CK  
D
OUT  
DATA REGISTER  
D
IN  
DS500074-1  
1
© 1999 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
NM24Wxx Rev. C.2  
Powered by ICminer.com Electronic-Library Service CopyRight 2003  

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