Datasheet > NM24C09LM8

NM24C09LM8

更新时间： 2024-02-09 09:58:13

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数	文件大小	规格书
10页	35K
描述
EEPROM, 1KX8, Serial, CMOS, PDSO8, PLASTIC, SOIC-8

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技术参数
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NM24C09LM8 技术参数

生命周期：	Active	零件包装代码：	SOIC
包装说明：	PLASTIC, SOIC-8	针数：	8
Reach Compliance Code：	unknown	风险等级：	5.82
其他特性：	16 BYTE PAGE WRITE MODE; DATA RETENTION > 40 YEARS	最大时钟频率 (fCLK)：	0.1 MHz
JESD-30 代码：	R-PDSO-G8	长度：	4.9 mm
内存密度：	8192 bit	内存集成电路类型：	EEPROM
内存宽度：	8	功能数量：	1
端子数量：	8	字数：	1024 words
字数代码：	1000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	1KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	SERIAL
认证状态：	COMMERCIAL	座面最大高度：	1.75 mm
串行总线类型：	I2C	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	2.7 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	3.9 mm	最长写入周期时间 (tWC)：	15 ms

NM24C09LM8 数据手册

Fairchild

Application Note 794

Using an EEPROM—

IIC Interface

NM24C02/03/04/05/08/09/

16/17

ration used by the IIC interface compared to that of the

MICROWIRE™ and SPI interface, reduced board space and pin

count allows the designer to have more creative flexibility while

reducing interconnecting cost.

INTRODUCTION

Fairchild Semiconductor’s NM24C EEPROMs are designed to

interface with Inter-Integrated Circuit (IIC) buses and hardware.

Fairchild’s electrically erasable programmable read only memo-

ries (EEPROMs) offer valuable security features (write protec-

tion), two write modes, three read modes and a wide variety of

memory sizes. Applications for the IIC bus and NM24C memories

are included in SANs (small-area networks), stereos, televisions,

automobiles and other scaled-down systems that don’t require

tremendous speeds but instead cost efficiency and design sim-

plicity.

OPERATING Fairchild SEMICONDUCTOR’S

NM24Cs

TheNM24CE²PROMsrequireonlysixsimpleoperatingcodesfor

transmittingorreceivingbitsofinformationoverthe2-wireIICbus.

These fields are explained in greater detail below and briefly

described hereafter: a start bit, a 7-bit slave address, a read/write

bit which defines whether the slave is a transmitter or receiver, an

acknowledge bit, message bits divided into 8-bit segments and a

stop bit.

IIC BACKGROUND

The IIC bus configuration is an amalgam of microcontrollers and

peripheral controllers. By definition: a device that transmits sig-

nalsontotheIICbusisthe“transmitter”andadevicethatreceives

signals is the “receiver”; a device that controls signal transfers on

thelineinadditiontocontrollingtheclockfrequencyisthe“master”

and a device that is controlled by the master is the “slave”. The

master can transmit or receive signals to or from a slave, respec-

tively, or control signal transfers between two slaves, where one

is the transmitter and the other is the receiver. It is possible to

combineseveralmasters,inadditiontoseveralslaves,ontoanIIC

bus to form a multimaster system. If more than one master

simultaneously tries to control the line, an arbitration procedure

decides which master gets priority. The maximum number of

devices connected to the bus is dictated by the maximum allow-

able capacitance on the lines, 400 pF, and the protocol’s address-

ing limit of 16k; typical device capacitance is 10 pF. Up to eight

E²PROMs can be connected to an IIC bus, depending on the size

of the memory device implemented.

For efficient and faster serial communication between devices,

the NM24C Family features page write and sequential read.

TheNM24C03/C05/C09/C16/C17Familyoffersasecurityfeature

in addition to standard features found in the NM24C02/C04/C08/

C16Family. Thesecurityfeatureisbeneficial inthatitallowsRead

Only Memory (ROM) to be implemented in the upper half of the

memory to prevent any future programming in that particular chip

section; the remaining memory that has not been write protected

can still be programmed. The security feature in the NM24C03/

C05/C09/C17 Family does not require immediate implementation

when the device is interfaced to the IIC bus, which gives the

designer the option to choose this feature at a later date. Table 1

displays the following parameters: memory content, write protect

and the maximum number of individual IIC E²PROMs allowed on

anIICbusatonetimeifthetotallinecapacitanceiskeptbelow400

pF.

CodeusedtointerfacetheNM24CswithFairchildSemiconductor’s

COP8™ Microcontroller Family is listed in a latter section of this

application note for further information to the reader.

Simplicity of the IIC system is primarily due to the bidirectional 2-

wire design, a serial data line (SDA) and serial clock line (SKL),

and to the protocol format. Because of the efficient 2-wire configu-

TABLE 1.

Number of

Part No.

Write Protect

Max.

256x8 Page Blocks

Feature

Parts

NM24C02

NM24C03

NM24C04

NM24C05

NM24C08

NM24C09

NM24C16

NM24C17

Yes

www.fairchildsemi.com

12 3 4 5 6 7...10

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与NM24C09LM8相关器件

型号	品牌	获取价格	描述	数据表
NM24C09LM8X	TI	获取价格	1KX8 I2C/2-WIRE SERIAL EEPROM, PDSO8, PLASTIC, SOP-8
NM24C09LMT8	FAIRCHILD	获取价格	I2C Serial EEPROM
NM24C09LMT8X	FAIRCHILD	获取价格	暂无描述
NM24C09LN	TI	获取价格	1KX8 I2C/2-WIRE SERIAL EEPROM, PDIP8, PLASTIC, DIP-8
NM24C09LN	FAIRCHILD	获取价格	I2C Serial EEPROM
NM24C09LVM8	FAIRCHILD	获取价格	I2C Serial EEPROM
NM24C09LVM8X	FAIRCHILD	获取价格	EEPROM, 1KX8, Serial, CMOS, PDSO8, PLASTIC, SOIC-8
NM24C09LVMT8	FAIRCHILD	获取价格	I2C Serial EEPROM
NM24C09LVN	FAIRCHILD	获取价格	I2C Serial EEPROM
NM24C09LZEM8	FAIRCHILD	获取价格	I2C Serial EEPROM

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