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NLX2G00EMUTCG PDF预览

NLX2G00EMUTCG

更新时间: 2024-12-01 20:00:07
品牌 Logo 应用领域
安森美 - ONSEMI 输入元件光电二极管逻辑集成电路触发器
页数 文件大小 规格书
10页 130K
描述
IC 2G SERIES, DUAL 2-INPUT NAND GATE, PDSO8, 1.60 X 1 MM, 0.40 MM PITCH, LEAD FREE, UDFN-8, Gate

NLX2G00EMUTCG 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DFN包装说明:1.60 X 1 MM, 0.40 MM PITCH, LEAD FREE, UDFN-8
针数:8Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.83
系列:2GJESD-30 代码:R-PDSO-N8
长度:1.6 mm负载电容(CL):15 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.004 A
功能数量:2输入次数:2
端子数量:8最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:VSON封装等效代码:SOLCC8,.04,16
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
包装方法:TAPE AND REEL电源:1.8/5 V
Prop。Delay @ Nom-Sup:11 ns传播延迟(tpd):10.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:0.55 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:0.4 mm
端子位置:DUAL宽度:1 mm
Base Number Matches:1

NLX2G00EMUTCG 数据手册

 浏览型号NLX2G00EMUTCG的Datasheet PDF文件第2页浏览型号NLX2G00EMUTCG的Datasheet PDF文件第3页浏览型号NLX2G00EMUTCG的Datasheet PDF文件第4页浏览型号NLX2G00EMUTCG的Datasheet PDF文件第5页浏览型号NLX2G00EMUTCG的Datasheet PDF文件第6页浏览型号NLX2G00EMUTCG的Datasheet PDF文件第7页 
NLX2G00  
Dual 2-Input NAND Gate  
The NLX2G00 is an advanced high-speed dual 2-input CMOS  
NAND gate in ultra-small footprint.  
The NLX2G00 input structures provide protection when voltages up  
to 7.0 volts are applied, regardless of the supply voltage.  
http://onsemi.com  
MARKING  
Features  
High Speed: t 2.4 ns (typical) at V = 5.0 V  
PD  
CC  
DIAGRAMS  
Designed for 1.65 V to 5.5 V V Operation  
CC  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
ULLGA8  
1.45 x 1.0  
CASE 613AA  
QM  
G
24 mA Balanced Output Sink and Source Capability  
Balanced Propagation Delays  
1
Overvoltage Tolerant (OVT) Input Pins  
This is a PbFree Device  
ULLGA8  
1.6 x 1.0  
CASE 613AB  
AJM  
G
1
ULLGA8  
1.95 x 1.0  
CASE 613AC  
AHM  
G
A1  
B1  
1
2
3
4
8
7
6
5
V
CC  
1
UDFN8  
1.45 x 1.0  
CASE 517BZ  
X M  
Y1  
B2  
A2  
1
UDFN8  
1.6 x 1.0  
CASE 517BY  
Y2  
IEEE/IEC  
&
X M  
X M  
A1  
B1  
1
Y1  
Y2  
A2  
B2  
GND  
UDFN8  
1.95 x 1.0  
CASE 517CA  
1
Figure 2. Logic Symbol  
Figure 1. Pinout  
XX  
M
G
= Specific Device Code  
= Date Code  
= PbFree Package  
PIN ASSIGNMENT  
FUNCTION TABLE  
Y = AB  
Pin  
Function  
1
A1  
Inputs  
Output  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
2
3
4
5
6
7
8
B1  
Y2  
A
L
B
L
Y
H
H
H
L
GND  
A2  
L
H
L
H
H
B2  
H
Y1  
H = HIGH Logic Level  
L = LOW Logic Level  
V
CC  
© Semiconductor Components Industries, LLC, 2012  
1
Publication Order Number:  
January, 2012 Rev. 1  
NLX2G00/D  

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