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NLSX3018DTR2G PDF预览

NLSX3018DTR2G

更新时间: 2024-11-02 05:53:59
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器
页数 文件大小 规格书
12页 166K
描述
8-Bit 100 Mb/s Configurable Dual-Supply Level Translator

NLSX3018DTR2G 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:TSSOP包装说明:TSSOP-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:4 weeks
风险等级:1.59Samacsys Description:Translation - Voltage Levels 8 BIT TRANSLATOR
系列:3018JESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
逻辑集成电路类型:BUS DRIVER湿度敏感等级:1
位数:4功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):9.3 ns
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):4.5 V最小供电电压 (Vsup):1.3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mm

NLSX3018DTR2G 数据手册

 浏览型号NLSX3018DTR2G的Datasheet PDF文件第2页浏览型号NLSX3018DTR2G的Datasheet PDF文件第3页浏览型号NLSX3018DTR2G的Datasheet PDF文件第4页浏览型号NLSX3018DTR2G的Datasheet PDF文件第5页浏览型号NLSX3018DTR2G的Datasheet PDF文件第6页浏览型号NLSX3018DTR2G的Datasheet PDF文件第7页 
NLSX3018  
8-Bit 100 Mb/s Configurable  
Dual-Supply Level  
Translator  
The NLSX3018 is a 8bit configurable dualsupply bidirectional  
level translator without a direction control pin. The I/O V and I/O  
http://onsemi.com  
CC  
V ports are designed to track two different power supply rails, V  
L
CC  
MARKING  
DIAGRAMS  
and V respectively. The V supply rail is configurable from 1.3 V  
L
CC  
to 4.5 V while the V supply rail is configurable from 0.9 V to (V  
L
CC  
0.4) V. This allows lower voltage logic signals on the V side to be  
L
UQFN20  
MU SUFFIX  
CASE 517AK  
LAM  
G
translated into higher voltage logic signals on the V  
side, and  
CC  
viceversa. Both I/O ports are autosensing; thus, no direction pin is  
required.  
The Output Enable (EN) input, when Low, disables both I/O ports  
by putting them in 3state. This significantly reduces the supply  
LA = Specific Device Code  
M
= Date Code  
G
= PbFree Package  
currents from both V and V . The EN signal is designed to track  
CC  
L
V .  
L
20  
SOIC20  
DW SUFFIX  
CASE 751D  
Features  
NLSX3018  
AWLYYWWG  
Wide HighSide V Operating Range: 1.3 V to 4.5 V  
CC  
Wide LowSide V Operating Range: 0.9 V to (V 0.4) V  
L
CC  
1
HighSpeed with 100 Mb/s Guaranteed Date Rate for V > 1.6 V  
Low BittoBit Skew  
Overvoltage Tolerant Enable and I/O Pins  
Nonpreferential Powerup Sequencing  
Small packaging: 4.0 mm x 2.0 mm UQFN20  
This is a PbFree Device  
L
A
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
WL  
YY  
WW  
G
NLSX  
TSSOP20  
DT SUFFIX  
CASE 948E  
Typical Applications  
Mobile Phones, PDAs, Other Portable Devices  
3018  
ALYWG  
G
PIN ASSIGNMENT  
A
L
Y
W
G
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
I/O V 1  
I/O V  
I/O V  
I/O V  
1
1
2
20  
19  
18  
L
CC  
I/O V 2  
2
CC  
3
CC  
4
CC  
L
3
I/O V 3  
L
(Note: Microdot may be in either location)  
I/O V 4  
4
17 I/O V  
L
V
V
CC  
5
16  
15  
L
EN  
6
GND  
I/O V  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
I/O V 5  
5
CC  
6
CC  
7
CC  
8
CC  
7
14  
L
I/O V 6  
8
13 I/O V  
L
9
12  
11  
I/O V 7  
I/O V  
I/O V  
L
10  
I/O V 8  
L
(Top View)  
©
Semiconductor Components Industries, LLC, 2009  
1
Publication Order Number:  
June, 2009 Rev. 0  
NLSX3018/D  

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