Datasheet > NJU8725

NJU8725

更新时间： 2024-11-08 22:32:51

品牌	Logo	应用领域
其他 - ETC		放大器
页数	文件大小	规格书
13页	160K
描述
CLASS D AMPLIFIER FOR DIGITAL AUDIO

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中文翻译

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数据手册

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NJU8725 数据手册

NJU8725

PRELIMINARY

CLASS D AMPLIFIER FOR DIGITAL AUDIO

ꢀ GENERAL DESCRIPTION

ꢀ PACKAGE OUTLINE

The NJU8725 is an 800mW-output class D

Amplifier featuring 6^th∆Σ modulation. It includes

Digital Attenuator, Mute, and De-emphasis circuits. It

converts Digital source input to PWM signal output

which is output PWM signal converted to analog

signal with simple external LC Filter. The NJU8725

realizes very high power-efficiency by class D

operation. Therefore, it is suitable for battery-powered

applications and others.

NJU8725V

ꢀ FEATURES

ꢀ PIN CONFIGURATION

ꢁ Stereo BTL Power Amplifier

ꢁ Sixth-order 32f_SOver Sampling ∆Σ & PWM

ꢁ Internal 8f_SOver Sampling Digital Filter

ꢁ Sampling Frequency : 96kHz (Max.)

V_DD

STBY

TEST

F0/DATA

F1/REQ

F2/SCK

DIN

ꢁ De-Emphasis

ꢁ System Clock

ꢁ Digital Processing

: 32kHz, 44.1kHz, 48kHz

MUTE

: 256f_S

V_DDL

V_DDR

: Attenuator 107step, LOG Curve

: Mute

OUT_LP

V_SSL

OUT_RP

V_SSR

OUT_RN

V_DDR

LRCK

BCK

ꢁ Digital Audio Interface : 16bit, 18bit

: I²S, LSB Justified, MSB Justified

OUT_LN

ꢁ Short Circuit Protection

V_DDL

ꢁ Operating Voltage

ꢁ Driving Voltage

: 3.0 to 3.6V

: V_DDto 5.25V

MODE

RST

ꢁ C-MOS Technology

ꢁ Package Outline

: SSOP24

V_SS

MCK

ꢀ BLOCK DIAGRAM

V_DD

Short Circuit

Protection

Power On

Reset Circuit

V_SS

V_DDL

Synchronization

Circuit

RST

OUT_LP

V_SSL

V_DDL

MCK

32f_S6^th∆Σ

LRCK

BCK

DIN

Serial

8f_S

OUT_LN

Audio Data

Interface

Over Sampling

Digital Filter

PWM

V_SSL

V_DDR

OUT_RP

MUTE

STBY

MODE

F0/DATA

F1/REQ

F2/SCK

V_SSR

V_DDR

System

Control

OUT_RN

V_SSR

- 1 -

12 3 4 5 6 7...13

中文翻译

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