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NFE31PT221D1E9B PDF预览

NFE31PT221D1E9B

更新时间: 2024-11-11 20:53:15
品牌 Logo 应用领域
村田 - MURATA LTE
页数 文件大小 规格书
62页 472K
描述
Data Line Filter, 1 Function(s), 25V, 6A, EIA STD PACKAGE SIZE 1206, 3 PIN

NFE31PT221D1E9B 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:ActiveReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8504.50.80.00
风险等级:5.78其他特性:T-TYPE CIRCUIT; BUILT-IN FERRITE BEAD
电容:220 µF滤波器类型:DATA LINE FILTER
高度:1.6 mm最小绝缘电阻:1000 M Ω
JESD-609代码:e3/e4长度:3.2 mm
安装类型:SURFACE MOUNT功能数量:1
最高工作温度:85 °C最低工作温度:-40 °C
包装方法:BULK物理尺寸:L3.2XB1.6XH1.6 (mm)/L0.126XB0.063XH0.063 (inch)
额定电流:6 A额定电压:25 V
端子面层:TIN/SILVER宽度:1.6 mm
Base Number Matches:1

NFE31PT221D1E9B 数据手册

 浏览型号NFE31PT221D1E9B的Datasheet PDF文件第2页浏览型号NFE31PT221D1E9B的Datasheet PDF文件第3页浏览型号NFE31PT221D1E9B的Datasheet PDF文件第4页浏览型号NFE31PT221D1E9B的Datasheet PDF文件第5页浏览型号NFE31PT221D1E9B的Datasheet PDF文件第6页浏览型号NFE31PT221D1E9B的Datasheet PDF文件第7页 
MAX 7000  
Programmable Logic  
Device Family  
®
March 2001, ver. 6.1  
Data Sheet  
High-performance, EEPROM-based programmable logic devices  
(PLDs) based on second-generation MAX® architecture  
5.0-V in-system programmability (ISP) through the built-in  
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in  
MAX 7000S devices  
Features...  
ISP circuitry compatible with IEEE Std. 1532  
Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S  
devices  
Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S  
devices with 128 or more macrocells  
Complete EPLD family with logic densities ranging from 600 to  
5,000 usable gates (see Tables 1 and 2)  
5-ns pin-to-pin logic delays with up to 175.4-MHz counter  
frequencies (including interconnect)  
PCI-compliant devices available  
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V  
MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family  
Data Sheet or the MAX 7000B Programmable Logic Device Family Data  
Sheet.  
f
Table 1. MAX 7000 Device Features  
Feature  
EPM7032  
EPM7064  
EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E  
Usable  
600  
1,250  
1,800  
2,500  
3,200  
3,750  
5,000  
gates  
Macrocells  
32  
2
64  
4
96  
6
128  
8
160  
10  
192  
12  
256  
16  
Logic array  
blocks  
Maximum  
36  
68  
76  
100  
104  
124  
164  
user I/O pins  
t
t
t
t
f
(ns)  
(ns)  
6
5
6
5
7.5  
6
7.5  
6
10  
12  
7
12  
7
PD  
SU  
7
3
(ns)  
2.5  
4
2.5  
4
3
3
3
3
FSU  
CO1  
CNT  
(ns)  
4.5  
125.0  
4.5  
125.0  
5
6
6
(MHz)  
151.5  
151.5  
100.0  
90.9  
90.9  
Altera Corporation  
1
A-DS-M7000-06.1  
 

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