NDDL1N60Z, NDTL1N60Z
Product Preview
N-Channel Power MOSFET
600 V, 15 W
Features
http://onsemi.com
• 100% Avalanche Tested
• These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
V
R
MAX
DS(ON)
(BR)DSS
Compliant
600 V
15 W @ 10 V
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
N−Channel MOSFET
D (2)
Parameter
Drain−to−Source Voltage
Continuous Drain Current R
Symbol
V
NDD
NDT
Unit
V
600
DSS
I
D
0.8
0.5
0.3
A
q
JC
Steady State, T = 25°C (Note 1)
C
Continuous Drain Current R
Steady State, T = 100°C (Note 1)
I
D
0.15
A
q
JC
G (1)
C
Pulsed Drain Current, t = 10 ms
I
3.2
25
1.0
3
A
p
DM
Power Dissipation – R
P
W
q
D
JC
S (3)
Steady State, T = 25°C
C
MARKING DIAGRAMS
Gate−to−Source Voltage
V
30
60
V
GS
4
Single Pulse Drain−to−Source
EAS
mJ
Drain
Avalanche Energy (I = 1.0 A)
PK
4
DPAK
CASE 369C
STYLE 2
Peak Diode Recovery (Note 2)
Source Current (Body Diode)
dv/dt
4.5
V/ns
A
I
0.5
0.3
2
1
S
3
Lead Temperature for Soldering
Leads
T
260
°C
L
2
Drain
1
3
Gate Source
Operating Junction and Storage
Temperature
T , T
−55 to +150
°C
J
STG
4
4
Drain
IPAK
CASE 369D
STYLE 2
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Limited by maximum junction temperature
1
2
3
2. I = 1.5 A, di/dt ≤ 100 A/ms, V ≤ BV
S
DD
DSS
Y
= Year
WW
G
= Work Week
= Pb−Free Package
THERMAL RESISTANCE
Parameter
1
2
3
Symbol
Value
Unit
°C/W
°C/W
Gate Drain Source
Junction−to−Case (Drain)
NDDL1N60Z
R
R
5
q
Drain
4
JC
JA
4
SOT−223
CASE 318E
STYLE 3
Junction−to−Ambient
(Note 4) NDDL1N60Z
(Note 3) NDDL1N60Z−1
(Note 4) NDTL1N60Z
(Note 5) NDTL1N60Z
50
96
62
151
q
AYW
L1N60ZG
G
1
2
3
A
Y
W
= Assembly Location
= Year
= Work Week
3. Insertion mounted.
1
2
3
4. Surface−mounted on FR4 board using 1” sq. pad size
Gate Drain Source
(Cu area = 1.127” sq. [2 oz] including traces).
01N60 = Specific Device Code
5. Surface−mounted on FR4 board using minimum recommended pad size
G
= Pb−Free Package
(Cu area = 0.026” sq. [2 oz]).
(*Note: Microdot may be in either location)
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
May, 2013 − Rev. P1
NDDL1N60Z/D