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NCP139AFCT180T2G

更新时间： 2024-11-20 02:48:19
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
9页 197K
描述
1 A, Very Low Dropout Bias Rail CMOS Voltage Regulator

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NCP139AFCT180T2G 数据手册

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NCP139  
1 A, Very Low Dropout Bias  
Rail CMOS Voltage  
Regulator  
The NCP139 is a 1 A VLDO equipped with NMOS pass transistor  
and a separate bias supply voltage (V ). The device provides very  
BIAS  
www.onsemi.com  
stable, accurate output voltage with low noise suitable for space  
constrained, noise sensitive applications. In order to optimize  
performance for battery operated portable applications, the NCP139  
T
MARKING  
DIAGRAM  
features low I consumption. The WLCSP6 1.2 mm x 0.8 mm Chip  
Q
Scale package is optimized for use in space constrained applications.  
WLCSP6, 1.2x0.8  
CASE 567MV  
XXMG  
Features  
• Input Voltage Range: V  
to 5.5 V  
OUT  
XX = Specific Device Code  
M
= Month Code  
• Bias Voltage Range: 3.0 V to 5.5 V  
G
= Pb−Free Package  
• Adjustable and Fixed Voltage Version Available  
• Output Voltage Range: 0.4 V to 1.8 V (Fixed)  
PIN CONNECTIONS  
Output Voltage Range: 0.5 V to 3.0 V (Adjustable)  
1
2
•
1% Accuracy over Temperature, 0.5% V  
@ 25°C  
OUT  
• Ultra−Low Dropout: Typ. 50 mV at 1 A  
• Very Low Bias Input Current of Typ. 35 mA  
A
B
C
VOUT  
VIN  
• Very Low Bias Input Current in Disable Mode: Typ. 0.5 mA  
• Logic Level Enable Input for ON/OFF Control  
• Output Active Discharge Option Available  
SNS/FB  
GND  
EN  
• Stable with a 10 mF Ceramic Capacitor  
• Available in WLCSP6 − 1.2 mm x 0.8 mm, 0.4 mm pitch Package  
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
Compliant  
VBIAS  
Typical Applications  
• Battery−powered Equipment  
• Smartphones, Tablets  
• Cameras, DVRs, STB and Camcorders  
Top View  
ORDERING INFORMATION  
See detailed ordering, marking and shipping information on  
page 7 of this data sheet.  
V
V
BIAS  
BIAS  
≥3.0 V  
≥3.0 V  
V
V
OUT  
OUT  
NCP139 − ADJ  
NCP139  
GND  
1 mF  
0.9 V up to 1 Adc,  
1.3 A peaks  
1 mF  
0.9 V up to 1 Adc,  
1.3 A peaks  
BIAS  
BIAS  
IN  
OUT  
FB  
OUT  
SNS  
R1  
R2  
V
IN  
V
IN  
IN  
10 mF  
10 mF  
EN  
EN  
4.7 mF  
4.7 mF  
GND  
V
V
EN  
EN  
Figure 1. Typical Application Schematics  
© Semiconductor Components Industries, LLC, 2017  
1
Publication Order Number:  
April, 2019 − Rev. 6  
NCP139/D  
1234567...9

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