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NB2309AI1HDTG PDF预览

NB2309AI1HDTG

更新时间: 2024-11-24 03:14:07
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 140K
描述
3.3 V Zero Delay Clock Buffer

NB2309AI1HDTG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.56Is Samacsys:N
系列:2309输入调节:STANDARD
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:5 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:16实输出次数:8
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:4.4 mm
最小 fmax:133.33 MHzBase Number Matches:1

NB2309AI1HDTG 数据手册

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NB2309A  
3.3 V Zero Delay  
Clock Buffer  
The NB2309A is a versatile, 3.3 V zero delay buffer designed to  
distribute highspeed clocks. It accepts one reference input and drives  
out nine lowskew clocks. It is available in a 16 pin package.  
The 1H version of the NB2309A operates at up to 133 MHz, and  
has higher drive than the 1 devices. All parts have onchip PLL’s that  
lock to an input clock on the REF pin. The PLL feedback is onchip  
and is obtained from the CLKOUT pad.  
http://onsemi.com  
MARKING  
DIAGRAMS*  
The NB2309A has two banks of four outputs each, which can be  
controlled by the Select inputs as shown in the Select Input Decoding  
Table. If all the output clocks are not required, Bank B can be  
threestated. The select inputs also allow the input clock to be directly  
applied to the outputs for chip and system testing purposes.  
Multiple NB2309A devices can accept the same input clock and  
distribute it. In this case the skew between the outputs of the two  
devices is guaranteed to be less than 700 ps.  
All outputs have less than 200 ps of cycletocycle jitter. The input  
and output propagation delay is guaranteed to be less than 350 ps, and  
the output to output skew is guaranteed to be less than 250 ps.  
The NB2309A is available in two different configurations, as shown  
in the ordering information table. The NB2309A1 is the base part. The  
NB2309Ax1H* is the high drive version of the 1 and its rise and fall  
times are much faster than 1 part.  
16  
1
16  
XXXXXXXXG  
AWLYWW  
1
SOIC16  
D SUFFIX  
CASE 751B  
16  
XXXX  
XXXX  
ALYWG  
G
16  
1
TSSOP16  
DT SUFFIX  
CASE 948F  
1
XXXX = Device Code  
= Assembly Location  
WL, L = Wafer Lot  
= Year  
A
Features  
Y
15 MHz to 133 MHz Operating Range, Compatible with CPU and  
PCI Bus Frequencies  
Zero Input Output Propagation Delay  
W, WW = Work Week  
G or G = PbFree Package  
*For additional marking information, refer to  
Application Note AND8002/D.  
Multiple LowSkew Outputs  
OutputOutput Skew Less than 250 ps  
DeviceDevice Skew Less than 700 ps  
One Input Drives 9 Outputs, Grouped as 4 + 4 + 1  
Less than 200 ps CycletoCycle Jitter is Compatible with PentiumR  
Based Systems  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
Test Mode to Bypass PLL  
Available in 16 Pin, 150 mil SOIC and 4.4 mm TSSOP  
3.3 V Operation, Advanced 0.35 CMOS Technology  
These are PbFree Devices**  
*x = C for Commercial; I for Industrial.  
**For additional information on our PbFree strategy and soldering details,  
please download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 Rev. 4  
NB2309A/D  

NB2309AI1HDTG 替代型号

型号 品牌 替代类型 描述 数据表
NB2309AI1HDTR2G ONSEMI

完全替代

3.3 V Zero Delay Clock Buffer
CY23EP09ZXC-1H CYPRESS

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2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer
CY2309CZXI-1H CYPRESS

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3.3V Zero Delay Clock Buffer

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