Datasheet > NB2304AC5HDTR2G

NB2304AC5HDTR2G

更新时间： 2023-01-02 18:41:39

品牌	Logo	应用领域
安森美 - ONSEMI		驱动光电二极管输出元件
页数	文件大小	规格书
12页	146K
描述
2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, LEAD FREE, TSSOP-8

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NB2304AC5HDTR2G 数据手册

NB2304A

3.3V Zero Delay

Clock Buffer

The NB2304A is a versatile, 3.3 V zero delay buffer designed to

distribute high−speed clocks in PC, workstation, datacom, telecom

and other high−performance applications. It is available in an 8 pin

package. The part has an on−chip PLL which locks to an input clock

presented on the REF pin. The PLL feedback is required to be driven

to FBK pin, and can be obtained from one of the outputs. The

input−to−output propagation delay is guaranteed to be less than

250 ps, and the output−to−output skew is guaranteed to be less than

200 ps.

The NB2304A has two Banks of two outputs each. Multiple

NB2304A devices can accept the same input clock and distribute it. In

this case, the skew between the outputs of the two devices is

guaranteed to be less than 500 ps.

The NB2304A is available in two different configurations (Refer to

NB2304A Configurations Table). The NB2304Ax1* is the base part,

where the output frequencies equal the reference if there is no counter

in the feedback path. The NB2304Ax1H is the high−drive version of

the −1 and the rise and fall times on this device are much faster.

The NB2304Ax2 allows the user to obtain REF, 1/2 X and 2X

frequencies on each output Bank. The exact configuration and output

frequencies depend on which output drives the feedback pin.

The NB2304Ax5H is a high−drive version with REF/2 on both

Banks.

http://onsemi.com

MARKING

DIAGRAMS*

SOIC−8

D SUFFIX

CASE 751

XXXX

ALYW

TSSOP−8

DT SUFFIX

CASE 948R

XXXX

ALYW

XXXX = Device Code

= Assembly Location

= Wafer Lot

= Year

= Work Week

Features

• Zero Input − Output Propagation Delay, Adjustable by Capacitive

Load on FBK Input

*For additional marking information, refer to

Application Note AND8002/D.

• Multiple Configurations − Refer to NB2304A Configurations Table

• Input Frequency Range: 10 MHz to 133 MHz

• Multiple Low−Skew Outputs

• Output−Output Skew < 200 ps

• Device−Device Skew < 500 ps

• Two Banks of Four Outputs

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

• Less than 200 ps Cycle−to−Cycle Jitter (−1, −1H, −5H)

• Available in Space Saving, 8 pin 150 mil SOIC Packages and

Standard TSSOP

• 3.3 V Operation

• Advanced 0.35 m CMOS Technology

• Industrial Temperature Available

• Pb−Free Packages are Available

*x = C for Commercial; I for Industrial.

Semiconductor Components Industries, LLC, 2005

Publication Order Number:

February, 2005 − Rev. 0

NB2304A/D

12 3 4 5 6 7...12

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与NB2304AC5HDTR2G相关器件

型号	品牌	获取价格	描述	数据表
NB2304AI1DG	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2304AI1DR2G	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2304AI1DT	ONSEMI	获取价格	IC 2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, TSS
NB2304AI1DTR2	ONSEMI	获取价格	2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, TSSOP-
NB2304AI1DTR2G	ONSEMI	获取价格	2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, LEAD F
NB2304AI1HDG	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2304AI1HDR2G	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2304AI1HDTR2	ONSEMI	获取价格	2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, TSSOP-
NB2304AI2D	ONSEMI	获取价格	2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150
NB2304AI2DG	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer

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