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NB2304AC2DR2G

更新时间： 2024-02-27 04:02:01
品牌 Logo 应用领域
安森美 - ONSEMI 时钟
页数 文件大小 规格书
10页 125K
描述
3.3 V Zero Delay Clock Buffer

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中文翻译

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NB2304AC2DR2G 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP,
针数：8Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.33
系列：2304输入调节：STANDARD
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：8
实输出次数：4最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.4 ns
座面最大高度：1.75 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9 mm最小 fmax：133.3 MHz
Base Number Matches：1

NB2304AC2DR2G 数据手册

 浏览型号NB2304AC2DR2G的Datasheet PDF文件第2页浏览型号NB2304AC2DR2G的Datasheet PDF文件第3页浏览型号NB2304AC2DR2G的Datasheet PDF文件第4页浏览型号NB2304AC2DR2G的Datasheet PDF文件第5页浏览型号NB2304AC2DR2G的Datasheet PDF文件第6页浏览型号NB2304AC2DR2G的Datasheet PDF文件第7页 
NB2304A  
3.3 V Zero Delay  
Clock Buffer  
The NB2304A is a versatile, 3.3 V zero delay buffer designed to  
distribute high−speed clocks in PC, workstation, datacom, telecom  
and other high−performance applications. It is available in an 8 pin  
package. The part has an on−chip PLL which locks to an input clock  
presented on the REF pin. The PLL feedback is required to be driven  
to FBK pin, and can be obtained from one of the outputs. The  
input−to−output propagation delay is guaranteed to be less than  
250 ps, and the output−to−output skew is guaranteed to be less than  
200 ps.  
http://onsemi.com  
MARKING  
DIAGRAM*  
8
The NB2304A has two Banks of two outputs each. Multiple  
NB2304A devices can accept the same input clock and distribute it. In  
this case, the skew between the outputs of the two devices is  
guaranteed to be less than 500 ps.  
XXXX  
ALYW  
G
SOIC−8  
D SUFFIX  
CASE 751  
8
1
1
The NB2304A is available in two different configurations (Refer to  
NB2304A Configurations Table). The NB2304Ax1* is the base part,  
where the output frequencies equal the reference if there is no counter  
in the feedback path. The NB2304Ax1H is the high−drive version of  
the −1 and the rise and fall times on this device are much faster.  
The NB2304Ax2 allows the user to obtain REF, 1/2 X and 2X  
frequencies on each output Bank. The exact configuration and output  
frequencies depend on which output drives the feedback pin.  
XXXX = Device Code  
A
L
Y
W
G
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
*For additional marking information, refer to  
Application Note AND8002/D.  
Features  
• Zero Input − Output Propagation Delay, Adjustable by Capacitive  
Load on FBK Input  
• Multiple Configurations − Refer to NB2304A Configurations Table  
• Input Frequency Range: 15 MHz to 133 MHz  
• Multiple Low−Skew Outputs  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
• Output−Output Skew < 200 ps  
• Device−Device Skew < 500 ps  
• Two Banks of Four Outputs  
• Less than 200 ps Cycle−to−Cycle Jitter (−1, −1H, −5H)  
• Available in Space Saving, 8 pin 150 mil SOIC Package  
• 3.3 V Operation  
• Advanced 0.35 m CMOS Technology  
• Industrial Temperature Available  
• These are Pb−Free Devices  
*x = C for Commercial; I for Industrial.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 5  
NB2304A/D  
1234567...10

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