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NAND512R4M5BZBE PDF预览

NAND512R4M5BZBE

更新时间: 2024-11-02 17:51:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 内存集成电路
页数 文件大小 规格书
22页 200K
描述
Memory Circuit, 64MX8, CMOS, PBGA149, 10 X 13.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TFBGA-149

NAND512R4M5BZBE 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:BGA包装说明:10 X 13.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TFBGA-149
针数:149Reach Compliance Code:compliant
HTS代码:8542.32.00.71风险等级:5.17
JESD-30 代码:R-PBGA-B149长度:13.5 mm
内存密度:536870912 bit内存集成电路类型:MEMORY CIRCUIT
内存宽度:8功能数量:1
端子数量:149字数:67108864 words
字数代码:64000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-30 °C
组织:64MX8封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):1.95 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:40
宽度:10 mmBase Number Matches:1

NAND512R4M5BZBE 数据手册

 浏览型号NAND512R4M5BZBE的Datasheet PDF文件第2页浏览型号NAND512R4M5BZBE的Datasheet PDF文件第3页浏览型号NAND512R4M5BZBE的Datasheet PDF文件第4页浏览型号NAND512R4M5BZBE的Datasheet PDF文件第5页浏览型号NAND512R4M5BZBE的Datasheet PDF文件第6页浏览型号NAND512R4M5BZBE的Datasheet PDF文件第7页 
NAND256-M  
NAND512-M, NAND01G-M  
256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND  
Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP  
PRELIMINARY DATA  
Feature summary  
Multi-Chip Packages  
FBGA  
– 1 die of 256 Mb, 512 Mb (x8/ x16) NAND  
Flash + 1 die of 256 Mb (x16) SDR  
LPSDRAM  
– 1 die of 256 Mb, 512 Mb (x8/ x16) NAND  
Flash + 2 dice of 256 Mb (x16) SDR  
LPSDRAMs  
TFBGA107 10.5 x 13 x 1.2mm  
TFBGA149 10 x 13.5 x 1.2mm  
LFBGA137 10.5 x 13 x 1.4mm  
– 1 die of 256 Mb, 512 Mb (x8/ x16) NAND  
Flash +1 die of 256 Mb (x16) DDR  
LPSDRAM  
– 1 die of 512 Mb (x16) NAND Flash + 1 die  
of 256 Mb or 512 Mb (x16) DDR LPSDRAM  
Fast Block Erase  
Supply voltages  
– Block erase time: 2ms (typ)  
– VDDF = 1.7V to 1.95V or 2.5V to 3.6V  
– VDDD = VDDQD = 1.7V to 1.9V  
Status Register  
Data integrity  
Electronic Signature  
ECOPACK® packages  
– 100,000 Program/Erase cycles  
– 10 years Data Retention  
Temperature range  
LPSDRAM  
– -30 to 85°C  
Interface: x16 bus width  
Deep Power Down mode  
1.8v LVCMOS interface  
Flash Memory  
NAND Interface  
– x8 or x16 bus width  
– Multiplexed Address/ Data  
Quad internal Banks controlled by BA0 and  
BA1  
Page size  
Automatic and controlled Precharge  
– x8 device: (512 + 16 spare) Bytes  
– x16 device: (256 + 8 spare) Words  
Auto Refresh and Self Refresh  
– 8,192 Refresh cycles/64ms  
Block size  
– Programmable Partial Array Self Refresh  
– x8 device: (16K + 512 spare) Bytes  
– x16 device: (8K + 256 spare) Words  
– Auto Temperature Compensated Self  
Refresh  
Page Read/Program  
Wrap sequence: sequential/interleave  
– Random access: 12µs (max)  
– Sequential access: 50ns (min)  
– Page program time: 200µs (typ)  
Burst Termination by Burst Stop command and  
Precharge command  
Copy Back Program mode  
– Fast page copy without external buffering  
May 2006  
Rev 4  
1/22  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to  
change without notice.  
www.st.com  
2

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