MX66C256
Very Low Power 32k x 8 CMOS SRAM
DESCRIPTION
FEATURES
The MX66C256 is a high performance, very low power
CMOS Static Random Access Memory organized as
32,768 words by 8 bits and operates at 5.0V supply
voltage.
Advanced CMOS technology and circuit techniques
provide both high speed and low power features with a
typical CMOS standby current of 0.4uA and maximum
access time of 70ns and 100 ns in 5V operation.
Easy memory expansion is provided by an active LOW
chip enable(CE), and active LOW output enable (OE)
and three-state output drivers.
The MX66C256 has an automatic power down feature,
reducing the power consumption significantly when chip
is deselected.
The MX66C256 is available in the JEDEC standard 28
pin 330mil Plastic SOP, and 8mmx13.4mm TSOP
(normal type).
Vcc operation voltage : 5.0V
Very low power consumption :
50 mA (Max.) write current
40 mA (Max.) read current
0.4uA (Typ.) CMOS standby current
High speed access time :
- 70
70ns (Max.)
- 100
100ns (Max.)
Input levels are CMOS-compatible
Automatic power down when chip is deselected
Three state outputs
Fully static operation
Data retention supply voltage as low as 2.0V
Easy expansion with CE and OE options
PIN CONFIGURATIONS
BLOCK DIAGRAM
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
2
3
A6
4
A5
A5
A6
5
A9
A4
6
A11
OE
A7
A3
7
Address
Memory Array
512 x 512
A12
A14
A13
A8
A9
18
512
A2
Row
8
28-SOP
A10
CE
Input
A1
9
Decoder
A0
Buffer
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
GND
A11
512
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
Column I/O
8
Write Driver
Sense Amp
8
8
Data
Output
Buffer
64
Column Decoder
12
OE
A11
A9
1
2
3
4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A8
CE
WE
OE
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
5
6
7
8
Control
Address Input Buffer
28-TSOP
Vdd
Gnd
A4 A3 A2 A1 A0 A10
9
10
11
12
13
14
A1
A2
P/N DS0035
Rev. 1.1, Jan., 2000
1
Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131
Tel (408)453-8088 Fax (408)451-0876 www.macronix.com