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MX27C8100PC-12 PDF预览

MX27C8100PC-12

更新时间: 2024-11-30 22:58:27
品牌 Logo 应用领域
旺宏电子 - Macronix 存储内存集成电路光电二极管OTP只读存储器
页数 文件大小 规格书
15页 498K
描述
8M-BIT [1M x8/512K x16] CMOS OTP ROM

MX27C8100PC-12 数据手册

 浏览型号MX27C8100PC-12的Datasheet PDF文件第2页浏览型号MX27C8100PC-12的Datasheet PDF文件第3页浏览型号MX27C8100PC-12的Datasheet PDF文件第4页浏览型号MX27C8100PC-12的Datasheet PDF文件第5页浏览型号MX27C8100PC-12的Datasheet PDF文件第6页浏览型号MX27C8100PC-12的Datasheet PDF文件第7页 
MX27C8100  
8M-BIT [1M x8/512K x16] CMOS OTP ROM  
FEATURES  
Operating current: 60mA  
Standby current: 100uA  
Package type:  
- 42 pin plastic DIP  
- 44 pin SOP  
1M x 8 or 512K x 16 organization  
+12.5V programming voltage  
Fast access time: 100/120/150/200 ns  
Totally static operation  
Completely TTL compatible  
GENERAL DESCRIPTION  
used. The MX27C8100 supports a intelligent fast pro-  
gramming algorithm which can result in programming  
time of less than two minutes.  
TheMX27C8100isa5Vonly,8M-bit,OneTimeProgram-  
mable Read Only Memory. It is organized as 1M x 8 or  
512K x 16, operates from a single + 5 volt supply, has  
a static standby mode, and features fast single address  
locationprogramming. AllprogrammingsignalsareTTL  
levels,requiringasinglepulse.Forprogrammingoutside  
fromthesystem,existingEPROMprogrammersmaybe  
This One Time Programmable Read Only Memory is  
packagedinindustrystandard42pindual-in-line plastic  
package and 44 pin SOP packages.  
PIN CONFIGURATIONS  
PDIP  
SOP  
NC  
NC  
A8  
A9  
NC  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A18  
A17  
A7  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
1
NC  
A18  
A17  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
A8  
2
A9  
3
A10  
A11  
A12  
A13  
A14  
A15  
A16  
BYTE/VPP  
GND  
Q15/A-1  
Q7  
A6  
4
A10  
A11  
A12  
A13  
A14  
A15  
A16  
BYTE/VPP  
GND  
Q15/A1  
Q7  
Q14  
Q6  
Q13  
Q5  
Q12  
Q4  
VCC  
A5  
5
A4  
6
A3  
7
A2  
8
A1  
9
A0  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
A0  
CE  
GND  
OE  
Q0  
Q8  
Q1  
Q9  
Q2  
Q10  
Q3  
Q11  
CE  
GND  
OE  
Q0  
Q8  
Q1  
Q9  
Q2  
Q10  
Q3  
Q11  
Q14  
Q6  
Q13  
Q5  
Q12  
Q4  
VCC  
BLOCK DIAGRAM  
CE  
Q0~Q14  
Q15/A-1  
CONTROL  
LOGIC  
OUTPUT  
OE  
BUFFERS  
BYTE/VPP  
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Y-DECODER  
X-DECODER  
Y-SELECT  
A0~A18  
8M BIT  
CELL  
ADDRESS  
INPUTS  
MAXTRIX  
VCC  
GND  
P/N: PM0261  
REV. 2.3, NOV. 12, 2001  
1

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