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MVTX2604AG PDF预览

MVTX2604AG

更新时间: 2024-10-27 22:12:55
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 网络接口电信电路以太网局域网(LAN)标准
页数 文件大小 规格书
173页 1994K
描述
Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch

MVTX2604AG 技术参数

是否Rohs认证:不符合生命周期:Transferred
包装说明:HBGA, BGA553(UNSPEC)Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.87
Is Samacsys:NJESD-30 代码:S-PBGA-B553
JESD-609代码:e0长度:37.5 mm
湿度敏感等级:1功能数量:1
端子数量:553最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HBGA封装等效代码:BGA553(UNSPEC)
封装形状:SQUARE封装形式:GRID ARRAY, HEAT SINK/SLUG
峰值回流温度(摄氏度):225电源:2.5,3.3 V
认证状态:Not Qualified座面最大高度:2.46 mm
子类别:Network Interfaces标称供电电压:2.5 V
表面贴装:YES技术:CMOS
电信集成电路类型:LAN SWITCHING CIRCUIT温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:37.5 mm
Base Number Matches:1

MVTX2604AG 数据手册

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MVTX2604  
Data Sheet  
Description  
The MVTX2604 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip  
provides 24 ports at 10/100 Mbps, 2 ports at 1000 Mbps and a CPU interface for managed and unmanaged switch  
applications. The Gigabit ports can also support 10/100 M and 2 G stacking modes.  
The chip supports up to 64 K MAC addresses and up to 255 port-based Virtual LANs (VLANs). The centralized  
shared memory architecture permits a very high performance packet forwarding rate at up to 9.524 M packets per  
second at full wire speed. The chip is optimized to provide low-cost, high-performance workgroup switching.  
Two Frame Buffer Memory domains utilize cost-effective, high-performance synchronous SRAM with aggregate  
bandwidth of 12.8 Gbps to support full wire speed on all ports simultaneously. In the 24+2 stacking (2 G per  
stacking port) configuration, 2 ZBT domains are needed.  
With delay bounded, strict priority, and/or WFQ transmission scheduling, and WRED dropping schemes, the  
MVTX2604 provides powerful QoS functions for various multimedia and mission-critical applications. The chip  
provides 4 transmission priorities (8 priorities per Gigabit port) and 2 levels of dropping precedence. Each packet is  
assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged  
frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The MVTX2604 recognizes a total of  
16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range).  
The MVTX2604 supports 3 groups of port trunking/load sharing. One group is dedicated to the two Gigabit ports,  
and the other two groups to 10/100 ports, where each 10/100 group can contain up to 4 ports. Port trunking/load  
sharing can be used to group ports between interlinked switches to increase the effective network bandwidth.  
In half-duplex mode all ports support backpressure flow control to minimize the risk of losing data during long  
activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The MVTX2604 also supports a per-  
system option to enable flow control for best effort frames, even on QoS-enabled ports.  
The Physical Coding Sublayer (PCS) is integrated on-chip to provide a direct 10-bit interface for connection to  
SERDES chips. The PCS can be bypassed to provide a GMII interface.  
Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are  
collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface.  
SNMP Management frames can be received and transmitted via the CPU interface creating a complete network  
management solution.  
The MVTX2604 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are  
capable of directly interfacing to LVTTL levels. The MVTX2604 is packaged in a 553-pin Ball Grid Array package.  
3
Zarlink Semiconductor Inc.  

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