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MVTX2601AG2 PDF预览

MVTX2601AG2

更新时间: 2024-11-11 19:46:27
品牌 Logo 应用领域
美高森美 - MICROSEMI 局域网开关
页数 文件大小 规格书
98页 565K
描述
DATACOM, LAN SWITCHING CIRCUIT, PBGA553, 37.50 X 37.50 MM, 2.33 MM HEIGHT, LEAD FRFEE, MS-034, HSBGA-553

MVTX2601AG2 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:HBGA,针数:553
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.53JESD-30 代码:S-PBGA-B553
JESD-609代码:e1长度:37.5 mm
功能数量:1端子数量:553
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HBGA
封装形状:SQUARE封装形式:GRID ARRAY, HEAT SINK/SLUG
认证状态:Not Qualified座面最大高度:2.46 mm
标称供电电压:2.5 V表面贴装:YES
电信集成电路类型:LAN SWITCHING CIRCUIT温度等级:INDUSTRIAL
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:37.5 mmBase Number Matches:1

MVTX2601AG2 数据手册

 浏览型号MVTX2601AG2的Datasheet PDF文件第2页浏览型号MVTX2601AG2的Datasheet PDF文件第3页浏览型号MVTX2601AG2的Datasheet PDF文件第4页浏览型号MVTX2601AG2的Datasheet PDF文件第5页浏览型号MVTX2601AG2的Datasheet PDF文件第6页浏览型号MVTX2601AG2的Datasheet PDF文件第7页 
MVTX2601  
Unmanaged 24-Port 10/100M Layer-2  
Ethernet Switch  
Data Sheet  
April 2006  
Features  
Integrated Single-Chip 10/100M Ethernet Switch  
Ordering Information  
• Twenty-four 10/100 Mbps auto-negotiating Fast  
Ethernet (FE) ports with RMII or GPSI (7WS)  
interface options per port  
MVTX2601AG  
MVTX2601AG2  
553 Pin HSBGA  
553 Pin HSBGA**  
Supports one Frame Data Buffer (FDB) memory  
domains (1 MB or 2 MB) with pipelined, sync-burst  
SRAM at 100 MHz  
**Pb Free Tin/Silver/Copper  
-40°C to 85°C  
• Applies centralized shared memory architecture  
L2 Switching  
• Per-queue weighted random early discard (WRED)  
with 2 drop precedence levels  
• MAC address self learning, up to 64K MAC  
addresses  
• Supports port-based VLAN  
• Scheduling using delay bounded (DB), strict priority  
(SP), and Weighted Fair Queuing (WFQ) disciplines  
• User controlled WRED thresholds  
• Buffer management: per-class, shared, and per-port  
buffer reservations  
High performance packet classification and  
switching at full-wire speed  
Classification based on:  
CPU access supports the following interface  
options:  
• Serial interface in unmanaged mode, with optional  
I2C EEPROM support  
• Port-based priority: priority in a frame can be  
overwritten by the priority of port  
• VLAN Priority field in VLAN tagged frame (IEEE  
802.1p)  
Supports Ethernet multicasting and broadcasting  
and flooding control  
• DS/TOS field in IP packet  
• UDP/TCP logical ports: 8 hard-wired and 8  
programmable ports, including one programmable  
range  
Supports per-system option to enable flow  
control for best effort frames even on QoS-  
enabled ports  
The drop precedence of the above classifications  
is programmable  
QoS Support  
• 4 transmission priorities for Fast Ethernet ports  
Frame Data Buffer A  
SRAM (1M / 2M)  
FDB Interface  
LED  
Search  
Engine  
MCT  
Link  
Frame Engine  
24 x 10/100M  
FCB  
Management  
Module  
Serial  
RMII  
Ports 0 - 23  
Figure 1 - System Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.  

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