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MU9C8481L-10DC

更新时间： 2024-01-14 15:59:12
品牌 Logo 应用领域
MUSIC 存储内存集成电路静态存储器双倍数据速率局域网
页数 文件大小 规格书
20页 112K
描述
LANCAM㈢ 1ST Family

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MU9C8481L-10DC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Contact Manufacturer零件包装代码：LCC
包装说明：QCCJ, LDCC44,.7SQ针数：44
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.85
Is Samacsys：N最长访问时间：100 ns
JESD-30 代码：S-PQCC-J44JESD-609代码：e0
内存密度：524288 bit内存集成电路类型：CONTENT ADDRESSABLE SRAM
内存宽度：64湿度敏感等级：3
功能数量：1端子数量：44
字数：8192 words字数代码：8000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：8KX64
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC44,.7SQ封装形状：SQUARE
封装形式：CHIP CARRIER并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified最大待机电流：0.002 A
子类别：SRAMs最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

MU9C8481L-10DC 数据手册

 浏览型号MU9C8481L-10DC的Datasheet PDF文件第1页浏览型号MU9C8481L-10DC的Datasheet PDF文件第3页浏览型号MU9C8481L-10DC的Datasheet PDF文件第4页浏览型号MU9C8481L-10DC的Datasheet PDF文件第5页浏览型号MU9C8481L-10DC的Datasheet PDF文件第6页浏览型号MU9C8481L-10DC的Datasheet PDF文件第7页 
LANCAM 1ST Family  
GENERAL DESCRIPTION  
The LANCAM 1ST family consists of high density content-  
addressable memories (CAMs) in a variety of depths. Like the  
other LANCAM series from MUSIC Semiconductors, the  
LANCAM 1ST is ideal for time critical applications requiring  
intensive list processing.  
searches large databases for matching data in a short, constant  
time period, no matter how many entries are in the database.  
The ability to search data words up to 64 bits wide allows large  
address spaces to be searched rapidly and efficiently. A  
patented architecture links each CAM entry to associated data  
and makes this data available for use after a successful  
compare operation.  
Content-addressable memories, also known as associative  
memories, operate in the converse way to random access  
memories (RAM). In RAM, the input to the device is an address  
and the output is the data stored at that address. In CAM, the  
input is a data sample and the output is a flag to indicate a  
match and the address of the matching data. As a result, CAM  
The MUSIC LANCAM 1ST is ideal for address filtering and  
translation applications in LAN switches and routers. The  
LANCAM 1ST is also well suited to encryption, data caches,  
and branch tables.  
OPERATIONAL OVERVIEW  
To use the LANCAM 1ST, the user loads the data into the  
Comparand register, which is automatically compared to all  
valid CAM locations. The device then indicates whether  
or not one or more of the valid CAM locations contains  
data that match the target data. The status of each CAM  
location is determined by two validity bits at each memory  
location. The two bits are encoded to render four validity  
conditions: Valid, Skip, Empty, and Random Access, as  
shown in Table 1. The memory can be partitioned into CAM  
and associated RAM segments on 16-bit boundaries, but  
by using one of the two available mask registers, the  
CAM/RAM partitioning can be set at any arbitrary size  
between zero and 64 bits.  
automatically triggers a compare. Compares may also be  
initiated by a command to the device. Associated RAM  
data is available immediately after a successful compare  
operation. The Status register reports the results of  
compares including all flags and addresses. Two Mask  
registers are available and can be used in two different  
ways: to mask comparisons or to mask data writes. The  
random access validity type allows additional masks to  
be stored in the CAM array where they may be retrieved rapidly.  
A simple three-wire control interface and commands  
loaded into the Instruction decoder control the device.  
A powerful instruction set increases the control flexibility  
and minimizes software overhead. These and other  
features make the LANCAM 1ST a powerful associative  
memory that drastically reduces search delays.  
The LANCAM 1ST’s internal data path is 64 bits wide for  
rapid internal comparison and data movement. Loading data  
to the Control, Comparand, and mask registers  
Skip Bit  
Empty Bit  
Entry Type  
Valid  
0
0
1
1
0
1
0
1
Empty  
Skip  
GND  
D Q4  
D Q 5  
VCC  
VCC  
7
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
NC  
/MF  
8
RAM  
VCC  
GND  
/R  
9
10  
11  
12  
13  
14  
15  
16  
17  
Table 1: Entry Types vs. Validity Bits  
44-pin PLCC  
(Top View )  
TEST2  
GND  
VCC  
VCC  
TEST 1  
/E  
GND  
D Q6  
/W  
D Q7  
VCC  
GND  
/W  
/CM  
LOW  
HIGH  
LOW  
HIGH  
Cycle Type  
LOW  
LOW  
HIGH  
HIGH  
Command Write Cycle  
Data Write Cycle  
Command Read Cycle  
Data Read Cycle  
Table 2: I/O Cycles  
Pinout Diagram  
Rev. 1a  
2
1234567...20

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