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MU9C8481L-10DC PDF预览

MU9C8481L-10DC

更新时间： 2024-01-02 05:27:28
品牌 Logo 应用领域
MUSIC 存储内存集成电路静态存储器双倍数据速率局域网
页数 文件大小 规格书
20页 112K
描述
LANCAM㈢ 1ST Family

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MU9C8481L-10DC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Contact Manufacturer零件包装代码：LCC
包装说明：QCCJ, LDCC44,.7SQ针数：44
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.85
Is Samacsys：N最长访问时间：100 ns
JESD-30 代码：S-PQCC-J44JESD-609代码：e0
内存密度：524288 bit内存集成电路类型：CONTENT ADDRESSABLE SRAM
内存宽度：64湿度敏感等级：3
功能数量：1端子数量：44
字数：8192 words字数代码：8000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：8KX64
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC44,.7SQ封装形状：SQUARE
封装形式：CHIP CARRIER并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified最大待机电流：0.002 A
子类别：SRAMs最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

MU9C8481L-10DC 数据手册

 浏览型号MU9C8481L-10DC的Datasheet PDF文件第4页浏览型号MU9C8481L-10DC的Datasheet PDF文件第5页浏览型号MU9C8481L-10DC的Datasheet PDF文件第6页浏览型号MU9C8481L-10DC的Datasheet PDF文件第8页浏览型号MU9C8481L-10DC的Datasheet PDF文件第9页浏览型号MU9C8481L-10DC的Datasheet PDF文件第10页 
LANCAM 1ST Family  
OPERATIONAL CHARACTERISTICS Continued  
Cycle Type /E /CM /W I/O Status SPS SPD  
Operation  
Notes  
TCO  
Cmd Write  
L
L
L
IN  
IN  
IN  
Load Instruction decoder  
Load Address register  
Load Control register  
Load Segment Control register  
Read Next Free Address register  
Read Address register  
Read Status Register bits 15–0  
Read Status Register bits 31–16  
Read Control register  
Read Segment Control register  
Read Current Persistent Source or Destination 3,10  
Load Comparand register  
Load Mask Register 1  
1
2,3  
3
3
3
3
4
5
3
ü
ü
ü
ü
ü
IN  
Cmd Read  
L
L
H
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
IN  
IN  
IN  
IN  
IN  
ü
ü
ü
3
Data Write  
Data Read  
L
H
L
ü
ü
ü
ü
ü
ü
6,9  
7,9  
7,9  
7,9  
7,9  
7,9  
6, 9  
8, 9  
8, 9  
8, 9  
7, 8  
Load Mask Register 2  
Write Memory Array at address  
Write Memory Array at Next Free address  
Write Memory Array at Highest-Priority match  
Read Comparand register  
Read Mask Register 1  
Read Mask Register 2  
IN  
L
H
X
H
X
OUT  
OUT  
OUT  
OUT  
OUT  
ü
ü
ü
ü
ü
Read Memory Array at address  
Read Memory Array at Highest-Priority match  
H
HIGH-Z  
Deselected  
Notes:  
1. Default Command Write cycle destination (does not require a TCO instruction).  
2. Default Command Write cycle destination (no TCO instruction required) if Address Field flag was set in bit 11 of the  
instruction loaded in the previous cycle.  
3. Loaded or read on the Command Write or Read cycle immediately following a TCO instruction. Active for one Command Write  
or Read cycle only. NFA register cannot be loaded this way.  
4. Default Command Read cycle source (does not require a TCO instruction).  
5. Default Command Read cycle source (does not require a TCO instruction) if the previous cycle was a Command Read of  
Status Register bits 15–0. If next cycle is not a Command Read cycle, any subsequent Command Read cycle will access the  
Status Register bits 15–0.  
6. Default persistent source and destination on power-up and after Reset. If other resources were sources or destinations,  
SPD CR or SPS CR restores the Comparand register as the destination or source.  
7. Selected by executing a Select Persistent Destination instruction.  
8. Selected by executing a Select Persistent Source instruction.  
9. Access may require multiple 16-bit Read or Write cycles. The Segment Control register is used to control the selection of the  
desired 16-bit segment(s) by establishing the Segment counters’ start and end limits and count values.  
10. A Command Read cycle after a TCO PS or TCO PD reads back the Instruction decoder bits that were last set to select a  
persistant source or destination. The TCO PS instruction will also read back the Device ID.  
Table 3: Input/Output Operations  
Control Register bits CT3 and CT2 set the Address register to  
automatically increment or decrement (or not change) during  
sequences of Command or Data cycles. The Address register  
will change after executing an instruction that includes  
M@[AR] or M@aaaH, or after a data access to the end limit  
segment (as set in the Segment Control register) when the  
persistent source or destination is M@[AR] or M@aaaH.  
selected, and only the active Address register will be  
written to or read from.  
Next Free Address Register (NF)  
The LANCAM 1ST automatically stores the address of the  
first empty memory location in the Next Free Address register,  
which is then used as a memory address pointer for M@NF  
operations. The Next Free Address register, shown in Table 9  
on page 16, can be read using a TCO NF instruction. After a  
reset, the Next Free Address register is set to zero.  
Either the Foreground or Background Address register  
will be active, depending on which register set has been  
7
Rev. 1a  
1...45678910...20

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