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MU9C5640LF-70TZC PDF预览

MU9C5640LF-70TZC

更新时间: 2024-01-25 16:47:07
品牌 Logo 应用领域
MUSIC 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
22页 185K
描述
Content Addressable SRAM, 256X64, 70ns, CMOS, PQFP32

MU9C5640LF-70TZC 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
包装说明:QFP, QFP32,.35SQ,32Reach Compliance Code:unknown
风险等级:5.8最长访问时间:70 ns
JESD-30 代码:S-PQFP-G32内存密度:16384 bit
内存集成电路类型:CONTENT ADDRESSABLE SRAM内存宽度:64
湿度敏感等级:3端子数量:32
字数:256 words字数代码:256
最高工作温度:70 °C最低工作温度:
组织:256X64封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK
电源:3.3 V认证状态:Not Qualified
最大待机电流:0.002 A子类别:SRAMs
最大压摆率:0.03 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
Base Number Matches:1

MU9C5640LF-70TZC 数据手册

 浏览型号MU9C5640LF-70TZC的Datasheet PDF文件第13页浏览型号MU9C5640LF-70TZC的Datasheet PDF文件第14页浏览型号MU9C5640LF-70TZC的Datasheet PDF文件第15页浏览型号MU9C5640LF-70TZC的Datasheet PDF文件第17页浏览型号MU9C5640LF-70TZC的Datasheet PDF文件第18页浏览型号MU9C5640LF-70TZC的Datasheet PDF文件第19页 
LIST-XL Family  
Register Bit Assignments  
REGISTER BIT ASSIGNMENTS  
Device  
Bit(s)  
15  
Name  
Description  
0 = Reset  
Reserved  
RST  
14:9  
8:6  
0
CAM/RAM Part  
000 = 64 CAM/0 RAM  
001 = 48 CAM/16 RAM  
010 = 32 CAM/32 RAM  
011 = 16 CAM/48 RAM  
100 = 48 RAM/16 CAM  
101 = 32 RAM/32 CAM  
110 = 16 RAM/48 CAM  
111 = No Change  
All  
5:4  
3:2  
1:0  
Comp. Mask  
AR Inc/Dec  
0
00 = None  
01 = MR1  
10 = MR2  
11 = No Change  
00 = Increment  
01 = Decrement  
10 = Disable  
11 = No Change  
Reserved  
Table 7: Control Register Bits  
Note: D15 reads back as 0  
Device  
Bit(s)  
Name  
Description  
15  
SDL  
0 = Set Destination Segment Limits  
1 = No Change  
14:13  
12:11  
10  
DCSL  
DCEL  
SSL  
00–11 = Destination Count Start Limit  
00–11 = Destination Count End Limit  
0 = Set Source Segment Limits  
1 = No Change  
9:8  
7:6  
5
SCSL  
SCEL  
LDC  
00–11 = Source Count Start Limit  
00–11 = Source Count End Limit  
All  
0 = Load Destination Segment Count  
1 = No Change  
4:3  
2
DSCV  
LSC  
00–11 = Destination Seg. Count Value  
0 = Load Source Segment Count  
1 = No Change  
1:0  
SSCV  
00–11 = Source Segment Count Value  
Table 8: Segment Control Register Bits  
Note: D15, D10, D5, and D2 are read back as 0s.  
Device  
Bit(s)  
15:8  
7:0  
Name  
Description  
All 0’s  
Reserved  
NF7-0  
3640L(F)  
Next Free Address  
All 0’s  
15:9  
8:0  
Reserved  
NF8-0  
5640L(F)  
Next Free Address  
Table 9: Next Free Address Bits  
Note: The Next Free Address register is read only, and is accessed by performing a Command Read cycle immediately following a TCO  
NF Instruction.  
16  
Rev. 3.1  

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