Datasheet > 存储 > SRAM> MU9C16K64M-50B568C

MU9C16K64M-50B568C

更新时间： 2024-01-13 13:04:45

品牌	Logo	应用领域
MUSIC		存储内存集成电路静态存储器双倍数据速率
页数	文件大小	规格书
35页	1040K
描述
MU9C RCP Family

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技术参数
数据手册

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MU9C16K64M-50B568C 技术参数

是否Rohs认证：	不符合	生命周期：	Contact Manufacturer
包装说明：	BGA, BGA568,26X26,50	Reach Compliance Code：	unknown
风险等级：	5.88	Is Samacsys：	N
最长访问时间：	50 ns	JESD-30 代码：	S-PBGA-B568
JESD-609代码：	e0	内存密度：	1048576 bit
内存集成电路类型：	CONTENT ADDRESSABLE SRAM	内存宽度：	64
端子数量：	568	字数：	16384 words
字数代码：	16000	最高工作温度：	70 °C
最低工作温度：		组织：	16KX64
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA568,26X26,50	封装形状：	SQUARE
封装形式：	GRID ARRAY	电源：	3.3 V
认证状态：	Not Qualified	最大待机电流：	0.005 A
子类别：	SRAMs	最大压摆率：	0.9 mA
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
Base Number Matches：	1

MU9C16K64M-50B568C 数据手册

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MU9C RCP Family

Pin Descriptions

/FF (Full Flag, Output)

/RESET

The /FF output indicates when all the memory locations

have their Validity bits set valid (LOW). When there is at

least one location with its Validity bit set HIGH, the /FF

output will be HIGH; when all locations have their

Validity bits set LOW, and the /FI input is LOW, the /FF

output will be LOW. If the /FI input is HIGH, the /FF

output will be HIGH. The state of the /FF line will not

change until after the rising edge of /E during a Write

cycle.

The /RESET input is used to reset the MU9C RCP to a

known state. When the /RESET line is pulled LOW it

causes the MU9C RCP to enter its reset state. After power

is applied to the MU9C RCP, the /RESET line must be

held LOW for a time equal to or greater than the minimum

RESET pulse width before the device can operate

correctly. This pin is internally pulled up.

TCLK (JTAG Test Clock, Input)

The TCLK input is the Test Clock input. This pin is

internally pulled up.

/FI (Full Input, Input)

The /FI input receives full information from the next

higher-priority MU9C RCP in a vertically cascaded

system to provide system-level full information. When the

/FI input is LOW the /FF output will be HIGH if there is at

least one location whose Validity bit is set invalid; when

all locations have their Validity bits set valid, the /FF

output goes LOW. When the /FI input is HIGH, the /FF

output will remain HIGH. The /FF output from one device

is connected to the /FI input of the next lower-priority

device to give system-full indication. The /FI pin of the

highest-priority device must be tied LOW.

TMS (JTAG Test Mode Select, Input)

The TMS input is the Test Mode Select input. This pin is

internally pulled up.

TDI (JTAG Test Data Input, Input)

The TDI input is the Test Data input. This pin is internally

pulled up.

TDO (JTAG Test Data Output, Output)

The TCLK output is the Test Data Output. This pin is

internally pulled up.

/MM (Multiple Match, Open Drain Output)

/TRST (JTAG Reset, Input)

The /MM line indicates that there is a multiple match

within the system. When the /MI input is HIGH, the /MM

line is pulled LOW if there are at least two matches within

the MU9C RCP as a result of the previous Comparison

cycle; when there are less than two matches, the /MM line

floats HIGH. When the /MI input is LOW, the /MM line is

pulled LOW if there are one or more matches within the

MU9C RCP as a result of the previous Comparison cycle;

when there are no matches, the /MM line floats HIGH.

The /MM lines have open-drain outputs, so all /MM lines

within the system are connected together to give

system-level multiple match indication. The state of the

/MM line will not change until after the rising edge of /E

during a Comparison cycle.

The /TRST input is the Reset input, and serves to reset the

Test Access Port circuitry to its reset condition. This pin is

internally pulled up.

VDD, VDDIO, VSS (Positive Power Supply,

Ground)

These pins are the main power supply connections to the

MU9C RCP. VDD and VDDIO must be held at +3.3 Volts

and ± 0.3 Volts relative to the VSS pin, which is at 0 Volts,

system reference potential, for correct operation of the

device.

Note: The TCLK, TMS, TDI, TDO, and /TRST lines are defined

in the IEEE Standard Test Access Port and Boundary-scan

Architecture IEEE Standard. 1149.1-1990 and IEEE Standard.

1149.1a-1993.

Rev. 8.04

1...3 4 567 8 9...35

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